coreboot: move TS_END_ROMSTAGE to one spot

While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
     timestamp table.

Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/cpu/intel/haswell/romstage.c

@@ -274,7 +274,6 @@ void romstage_common(const struct romstage_params *params)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(wake_from_s3);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
 
 static inline void prepare_for_resume(struct romstage_handoff *handoff)

src/lib/prog_loaders.c

@@ -96,6 +96,8 @@ void run_ramstage(void)
 	struct prog ramstage =
 		PROG_INIT(ASSET_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage");
 
+	timestamp_add_now(TS_END_ROMSTAGE);
+
 	/* Only x86 systems currently take the same firmware path on resume. */
 	if (IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
 		run_ramstage_from_resume(romstage_handoff_find_or_add(),

src/mainboard/advansus/a785e-i/romstage.c

@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	rs780_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/amd/bimini_fam10/romstage.c

@@ -225,8 +225,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb800_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -333,8 +333,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //	die("After MCT init before CAR disabled.");
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/apple/macbook21/romstage.c

@@ -344,7 +344,4 @@ void main(unsigned long bist)
 
 	/* Initialize the internal PCIe links before we go into stage2 */
 	i945_late_initialization(s3resume);
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 }

src/mainboard/asus/kfsn4-dre/romstage.c

@@ -368,8 +368,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Restore default SuperIO access */
 	outb(0xaa, port);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }

src/mainboard/asus/m4a78-em/romstage.c

@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/asus/m4a785-m/romstage.c

@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/asus/m5a88-v/romstage.c

@@ -223,8 +223,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	rs780_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/avalue/eax-785e/romstage.c

@@ -227,8 +227,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	rs780_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/gigabyte/ma785gm/romstage.c

@@ -221,8 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -221,8 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/google/cosmos/romstage.c

@@ -53,7 +53,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }

src/mainboard/google/daisy/romstage.c

@@ -179,7 +179,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }

src/mainboard/google/link/romstage.c

@@ -247,6 +247,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/google/parrot/romstage.c

@@ -198,5 +198,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/google/peach_pit/romstage.c

@@ -278,7 +278,5 @@ void main(void)
 
 	simple_spi_test();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }

src/mainboard/google/stout/romstage.c

@@ -252,5 +252,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/google/veyron/romstage.c

@@ -111,7 +111,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }

src/mainboard/google/veyron_brain/romstage.c

@@ -102,7 +102,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }

src/mainboard/google/veyron_danger/romstage.c

@@ -106,7 +106,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }

src/mainboard/google/veyron_mickey/romstage.c

@@ -102,7 +102,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }

src/mainboard/google/veyron_rialto/romstage.c

@@ -112,7 +112,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }

src/mainboard/google/veyron_romy/romstage.c

@@ -102,7 +102,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -218,8 +218,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	bcm5785_early_setup();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();
 }
 

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/intel/cougar_canyon2/romstage.c

@@ -306,8 +306,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 	*(u32*)cbmem_hob_ptr = (u32)HobListPtr;
 	post_code(0x4f);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	while (1);

src/mainboard/intel/emeraldlake2/romstage.c

@@ -256,5 +256,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/jetway/pa78vm5/romstage.c

@@ -229,8 +229,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/kontron/ktqm77/romstage.c

@@ -243,5 +243,4 @@ void main(unsigned long bist)
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/lenovo/t60/romstage.c

@@ -284,6 +284,4 @@ void main(unsigned long bist)
 
 	/* Initialize the internal PCIe links before we go into stage2 */
 	i945_late_initialization(s3resume);
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/lenovo/x201/romstage.c

@@ -310,6 +310,4 @@ void main(unsigned long bist)
 #if CONFIG_LPC_TPM
 	init_tpm(s3resume);
 #endif
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/lenovo/x60/romstage.c

@@ -284,7 +284,4 @@ void main(unsigned long bist)
 
 	/* Initialize the internal PCIe links before we go into stage2 */
 	i945_late_initialization(s3resume);
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 }

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -243,8 +243,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }

src/mainboard/packardbell/ms2290/romstage.c

@@ -297,6 +297,4 @@ void main(unsigned long bist)
 		quick_ram_check();
 	}
 #endif
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/samsung/lumpy/romstage.c

@@ -274,5 +274,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/samsung/stumpy/romstage.c

@@ -284,5 +284,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -240,8 +240,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
 	post_code(0x42);     // Should never see this post code.
 }

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -304,8 +304,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();  /* BSP switch stack to ram, copy then execute CB. */
 	post_code(0x42);  /* Should never see this post code. */
 }

src/mainboard/supermicro/h8scm_fam10/romstage.c

@@ -239,8 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sr5650_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -239,8 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }

src/mainboard/via/epia-m850/romstage.c

@@ -96,7 +96,6 @@ void main(unsigned long bist)
 #if CONFIG_EARLY_CBMEM_INIT
 	cbmem_recovery(0);
 #endif
-	timestamp_add_now(TS_END_ROMSTAGE);
 	/* FIXME: See if this is needed or take this out please */
 	/* Disable Memcard and SDIO */
 	pci_mod_config8(LPC, 0x51, 0, (1 << 7) | (1 << 4));

src/northbridge/intel/sandybridge/romstage_native.c

@@ -135,5 +135,4 @@ void main(unsigned long bist)
 #endif
 
 	post_code(0x3f);
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/soc/intel/baytrail/romstage/romstage.c

@@ -250,8 +250,6 @@ void romstage_common(struct romstage_params *params)
 
 void asmlinkage romstage_after_car(void)
 {
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	while (1);

src/soc/intel/broadwell/romstage/romstage.c

@@ -132,8 +132,6 @@ void romstage_common(struct romstage_params *params)
 
 void asmlinkage romstage_after_car(void)
 {
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	while (1);

src/soc/intel/common/romstage.c

@@ -207,8 +207,6 @@ asmlinkage void romstage_after_car(void *chipset_context)
 	soc_after_temp_ram_exit();
 	soc_display_mtrrs();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	die("ERROR - Failed to load ramstage!");

src/soc/intel/fsp_baytrail/romstage/romstage.c

@@ -267,8 +267,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x4f);
 
 	/* Load the ramstage. */

src/southbridge/intel/fsp_rangeley/romstage.c

@@ -130,8 +130,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
 	post_code(0x4e);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x4f);
 
 	/* Load the ramstage. */