mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO.. - change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as EC_PCH_ARCORE_INT_L is active low - add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge BUG=b:139384979 BRANCH=none TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage", flash & boot nocturne in dev mode, verify that volume up and down buttons work in the dev screen and that the device boots properly into the kernel. Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -32,6 +32,9 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
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"EC in RW"},
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#ifdef EC_SYNC_GPIO
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{EC_SYNC_GPIO, ACTIVE_LOW, gpio_get(EC_SYNC_GPIO), "EC sync gpio"},
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#endif
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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@ -196,7 +196,7 @@ static const struct pad_config gpio_table[] = {
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/* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */
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PAD_CFG_GPO(GPP_D16, 0, DEEP),
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/* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */
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PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST),
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PAD_CFG_GPI_APIC_INVERT(GPP_D17, NONE, PLTRST),
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/* D18 : DMIC_DATA1 ==> TP131 */
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PAD_CFG_NC(GPP_D18),
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/* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */
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@ -34,9 +34,12 @@
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/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
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#define GPE_EC_WAKE GPE0_LAN_WAK
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/* EC sync irq is GPP_D12 */
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/* EC sync irq is tied to GPP_D17 */
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#define EC_SYNC_IRQ GPP_D17_IRQ
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/* EC sync gpio */
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#define EC_SYNC_GPIO GPP_D17
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/* eSPI virtual wire reporting */
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#define EC_SCI_GPI GPE0_ESPI
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