GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO 

Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO..

 - change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as
   EC_PCH_ARCORE_INT_L is active low

 - add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge

BUG=b:139384979
BRANCH=none
TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage",
flash & boot nocturne in dev mode, verify that volume up and down
buttons work in the dev screen and that the device boots properly into
the kernel.

Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Nick Vaccaro 2019-08-29 20:11:48 -07:00 committed by Patrick Georgi
parent 687c419cde
commit 98189771ab
3 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/poppy/chromeos.c
View File

@ -32,6 +32,9 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
"EC in RW"}, "EC in RW"},
#ifdef EC_SYNC_GPIO
{EC_SYNC_GPIO, ACTIVE_LOW, gpio_get(EC_SYNC_GPIO), "EC sync gpio"},
#endif
}; };
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
} }

2
src/mainboard/google/poppy/variants/nocturne/gpio.c
View File

@ -196,7 +196,7 @@ static const struct pad_config gpio_table[] = {
/* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */ /* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */
PAD_CFG_GPO(GPP_D16, 0, DEEP), PAD_CFG_GPO(GPP_D16, 0, DEEP),
/* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */ /* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */
PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST), PAD_CFG_GPI_APIC_INVERT(GPP_D17, NONE, PLTRST),
/* D18 : DMIC_DATA1 ==> TP131 */ /* D18 : DMIC_DATA1 ==> TP131 */
PAD_CFG_NC(GPP_D18), PAD_CFG_NC(GPP_D18),
/* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */

5
src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h
View File

@ -34,9 +34,12 @@
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK #define GPE_EC_WAKE GPE0_LAN_WAK
/* EC sync irq is GPP_D12 */ /* EC sync irq is tied to GPP_D17 */
#define EC_SYNC_IRQ GPP_D17_IRQ #define EC_SYNC_IRQ GPP_D17_IRQ
/* EC sync gpio */
#define EC_SYNC_GPIO GPP_D17
/* eSPI virtual wire reporting */ /* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI #define EC_SCI_GPI GPE0_ESPI