cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE

Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE".
It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets
should have at least 256K L2 cache. That is plenty for XIP RO cache of
bootblock + romstage and a 32K CAR.

Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/cpu/intel/socket_LGA775/Kconfig

@@ -17,7 +17,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
 
 config DCACHE_RAM_SIZE
 	hex
-	default 0x4000 # 16 kB
+	default 0x8000 # 32 kB
 
 config DCACHE_BSP_STACK_SIZE
 	hex

src/mainboard/asus/p5gc-mx/Kconfig

@@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_512
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select INTEL_GMA_HAVE_VBT
-	select NO_CBFS_MCACHE
 
 config MAINBOARD_DIR
 	string

src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig

@@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select REALTEK_8168_RESET if BOARD_GIGABYTE_GA_945GCM_S2L
 	select INTEL_GMA_HAVE_VBT
-	select NO_CBFS_MCACHE
 
 config MAINBOARD_DIR
 	string

src/northbridge/intel/x4x/Kconfig

@@ -13,7 +13,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select CACHE_MRC_SETTINGS
 	select PARALLEL_MP
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
-	select NO_CBFS_MCACHE
 
 config CBFS_SIZE
 	hex