cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm

C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.

This removes the need for a magic lapic in the devicetree.

Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/cpu/intel/model_1067x/chip.h

@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-struct cpu_intel_model_1067x_config {
-	int c5 : 1;
-	int c6 : 1;
-	int slfm : 1;
-};

src/cpu/intel/model_1067x/model_1067x_init.c

@@ -9,25 +9,18 @@
 #include <cpu/x86/name.h>
 #include <cpu/intel/smm_reloc.h>
 
-#include "chip.h"
-
 #define MSR_BBL_CR_CTL3		0x11e
 
 static void configure_c_states(const int quad)
 {
 	msr_t msr;
 
-	/* Find pointer to CPU configuration. */
-	const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-	const struct cpu_intel_model_1067x_config *const conf =
-		(lapic && lapic->chip_info) ? lapic->chip_info : NULL;
-
 	/* Is C5 requested and supported? */
-	const int c5 = conf && conf->c5 &&
+	const int c5 = southbridge_support_c5() &&
 			(rdmsr(MSR_BBL_CR_CTL3).lo & (3 << 30)) &&
 			!(rdmsr(MSR_FSB_FREQ).lo & (1 << 31));
 	/* Is C6 requested and supported? */
-	const int c6 = conf && conf->c6 &&
+	const int c6 = southbridge_support_c6() &&
 			((cpuid_edx(5) >> (6 * 4)) & 0xf) && c5;
 
 	const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */
@@ -75,14 +68,9 @@ static void configure_p_states(const char stepping, const char cores)
 {
 	msr_t msr;
 
-	/* Find pointer to CPU configuration. */
-	const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-	struct cpu_intel_model_1067x_config *const conf =
-		(lapic && lapic->chip_info) ? lapic->chip_info : NULL;
-
 	msr = rdmsr(MSR_EXTENDED_CONFIG);
 	/* Super LFM supported? */
-	if (conf && conf->slfm && (msr.lo & (1 << 27)))
+	if (northbridge_support_slfm() && (msr.lo & (1 << 27)))
 		msr.lo |= (1 << 28); /* Enable Super LFM. */
 	wrmsr(MSR_EXTENDED_CONFIG, msr);
 

src/include/cpu/intel/speedstep.h

@@ -3,11 +3,9 @@
 #ifndef CPU_INTEL_SPEEDSTEP_H
 #define CPU_INTEL_SPEEDSTEP_H
 
+#include <stdbool.h>
 #include <stdint.h>
 
-/* Magic value used to locate speedstep configuration in the device tree */
-#define SPEEDSTEP_APIC_MAGIC 0xACAC
-
 /* MWAIT coordination I/O base address. This must match
  * the \_PR_.CP00 PM base address.
  */
@@ -92,4 +90,8 @@ void speedstep_gen_pstates(sst_table_t *);
 #define SPEEDSTEP_MIN_POWER_PENRYN	15000
 #define SPEEDSTEP_SLFM_POWER_PENRYN	12000
 
+bool southbridge_support_c5(void);
+bool southbridge_support_c6(void);
+bool northbridge_support_slfm(void);
+
 #endif /* CPU_INTEL_SPEEDSTEP_H */

src/mainboard/acer/g43t-am3/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x	# CPU
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x		# CPU
-			device lapic 0xACAC off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x		# CPU
-			device lapic 0xACAC off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x		# CPU
-			device lapic 0xACAC off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x		# CPU
-			device lapic 0xACAC off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x		# CPU
-			device lapic 0xACAC off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asus/p5gc-mx/devicetree.cb

@@ -7,9 +7,6 @@ chip northbridge/intel/i945
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x
-			device lapic 0xACAC off end
-		end
 	end
 
 	device domain 0 on

src/mainboard/asus/p5qc/variants/p5q/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x		# CPU
-			device lapic 0xACAC off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x	# CPU
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x	# CPU
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x	# CPU
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x	# CPU
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asus/p5ql-em/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x		# CPU
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/asus/p5qpl-am/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x		# CPU
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/foxconn/g41s-k/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x		# CPU
-			device lapic 0xACAC off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb

@@ -7,9 +7,6 @@ chip northbridge/intel/i945
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x
-			device lapic 0xACAC off end
-		end
 	end
 
 	register "pci_mmio_size" = "768"

src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x	# CPU
-			device lapic 0xACAC off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/intel/dg41wv/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x		# CPU
-			device lapic 0xACAC off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/intel/dg43gt/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x	# CPU
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/lenovo/t400/devicetree.cb

@@ -8,22 +8,13 @@ chip northbridge/intel/gm45
 	register "gpu_panel_power_backlight_off_delay" = "2500"	# Tx:   250ms
 	register "gpu_panel_power_cycle_delay" = "3"		# T4:   200ms
 
+	register "slfm" = "1"
+
 	device cpu_cluster 0 on
 		ops gm45_cpu_bus_ops
 		chip cpu/intel/socket_p
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-
-			# Enable Super LFM
-			register "slfm" = "1"
-
-			# Enable C5, C6
-			register "c5" = "1"
-			register "c6" = "1"
-		end
 	end
 
 	register "pci_mmio_size" = "2048"

src/mainboard/lenovo/thinkcentre_a58/devicetree.cb

@@ -6,9 +6,6 @@ chip northbridge/intel/x4x		# Northbridge
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x		# CPU
-			device lapic 0xACAC off end
-		end
 	end
 	device domain 0 on
 		ops x4x_pci_domain_ops		# PCI domain

src/mainboard/lenovo/x200/devicetree.cb

@@ -8,22 +8,13 @@ chip northbridge/intel/gm45
 	register "gpu_panel_power_backlight_off_delay" = "2500"	# Tx:   250ms
 	register "gpu_panel_power_cycle_delay" = "3"		# T4:   200ms
 
+	register "slfm" = "1"
+
 	device cpu_cluster 0 on
 		ops gm45_cpu_bus_ops
 		chip cpu/intel/socket_BGA956
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-
-			# Enable Super LFM
-			register "slfm" = "1"
-
-			# Enable C5, C6
-			register "c5" = "1"
-			register "c6" = "1"
-		end
 	end
 
 	register "pci_mmio_size" = "2048"

src/mainboard/roda/rk9/devicetree.cb

@@ -1,22 +1,12 @@
 chip northbridge/intel/gm45
 	# IGD Displays
 	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+	register "slfm" = "1"
 	device cpu_cluster 0 on
 		ops gm45_cpu_bus_ops
 		chip cpu/intel/socket_BGA956
 			device lapic 0 on end
 		end
-		chip cpu/intel/model_1067x
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-
-			# Enable Super LFM
-			register "slfm" = "1"
-
-			# Enable C5, C6
-			register "c5" = "1"
-			register "c6" = "1"
-		end
 	end
 
 	register "pci_mmio_size" = "2048"

src/northbridge/intel/gm45/chip.h

@@ -19,6 +19,7 @@ struct northbridge_intel_gm45_config {
 	 * Maximum PCI mmio size in MiB.
 	 */
 	u16 pci_mmio_size;
+	int slfm;
 };
 
 #endif				/* NORTHBRIDGE_INTEL_GM45_CHIP_H */

src/northbridge/intel/gm45/northbridge.c

@@ -7,6 +7,7 @@
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
+#include <cpu/intel/speedstep.h>
 #include <cpu/intel/smm_reloc.h>
 #include <device/device.h>
 #include <device/pci_def.h>
@@ -257,3 +258,10 @@ struct chip_operations northbridge_intel_gm45_ops = {
 	CHIP_NAME("Intel GM45 Northbridge")
 	.init = gm45_init,
 };
+
+bool northbridge_support_slfm(void)
+{
+	struct device *gmch = __pci_0_00_0;
+	struct northbridge_intel_gm45_config *config = gmch->chip_info;
+	return config->slfm == 1;
+}

src/northbridge/intel/i945/northbridge.c

@@ -10,6 +10,7 @@
 #include <device/pci_ids.h>
 #include <acpi/acpi.h>
 #include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/speedstep.h>
 #include "i945.h"
 
 static void mch_domain_read_resources(struct device *dev)
@@ -164,3 +165,8 @@ struct device_operations i945_cpu_bus_ops = {
 struct chip_operations northbridge_intel_i945_ops = {
 	CHIP_NAME("Intel i945 Northbridge")
 };
+
+bool northbridge_support_slfm(void)
+{
+	return false;
+}

src/northbridge/intel/x4x/northbridge.c

@@ -12,6 +12,7 @@
 #include <northbridge/intel/x4x/chip.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/speedstep.h>
 
 static void mch_domain_read_resources(struct device *dev)
 {
@@ -194,3 +195,8 @@ struct chip_operations northbridge_intel_x4x_ops = {
 	CHIP_NAME("Intel 4-Series Northbridge")
 	.init = x4x_init,
 };
+
+bool northbridge_support_slfm(void)
+{
+	return false;
+}

src/southbridge/intel/i82801gx/lpc.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/intel/speedstep.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -473,3 +474,13 @@ static const struct pci_driver ich7_lpc __pci_driver = {
 	.vendor	= PCI_VID_INTEL,
 	.devices = pci_device_ids,
 };
+
+bool southbridge_support_c5(void)
+{
+	return false;
+}
+
+bool southbridge_support_c6(void)
+{
+	return false;
+}

src/southbridge/intel/i82801ix/lpc.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/intel/speedstep.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -137,6 +138,20 @@ static void i82801ix_gpi_routing(struct device *dev)
 	pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);
 }
 
+bool southbridge_support_c5(void)
+{
+	struct device *lpc_dev = __pci_0_1f_0;
+	struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info;
+	return config->c5_enable == 1;
+}
+
+bool southbridge_support_c6(void)
+{
+	struct device *lpc_dev = __pci_0_1f_0;
+	struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info;
+	return config->c6_enable == 1;
+}
+
 static void i82801ix_power_options(struct device *dev)
 {
 	u8 reg8;
@@ -216,15 +231,15 @@ static void i82801ix_power_options(struct device *dev)
 	reg16 |= (1 << 10);	// BIOS_PCI_EXP_EN - Desktop/Mobile only
 	if (CONFIG(DEBUG_PERIODIC_SMI))
 		reg16 |= (3 << 0); // Periodic SMI every 8s
-	if (config->c5_enable)
+	if (southbridge_support_c5())
 		reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */
 	pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16);
 
 	/* Set exit timings for C5/C6. */
-	if (config->c5_enable) {
+	if (southbridge_support_c5()) {
 		reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING);
 		reg8 &= ~((7 << 3) | (7 << 0));
-		if (config->c6_enable)
+		if (southbridge_support_c6())
 			reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#,
 							95-102us DPRSTP# to STP_CPU# */
 		else

src/southbridge/intel/i82801jx/lpc.c

@@ -13,6 +13,7 @@
 #include <arch/ioapic.h>
 #include <acpi/acpi.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/speedstep.h>
 #include <acpi/acpigen.h>
 #include <arch/smp/mpspec.h>
 #include "chip.h"
@@ -139,6 +140,20 @@ static void i82801jx_gpi_routing(struct device *dev)
 	pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);
 }
 
+bool southbridge_support_c5(void)
+{
+	struct device *lpc_dev = __pci_0_1f_0;
+	struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info;
+	return config->c5_enable == 1;
+}
+
+bool southbridge_support_c6(void)
+{
+	struct device *lpc_dev = __pci_0_1f_0;
+	struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info;
+	return config->c6_enable == 1;
+}
+
 static void i82801jx_power_options(struct device *dev)
 {
 	u8 reg8;
@@ -218,15 +233,15 @@ static void i82801jx_power_options(struct device *dev)
 	reg16 |= (1 << 10);	// BIOS_PCI_EXP_EN - Desktop/Mobile only
 	if (CONFIG(DEBUG_PERIODIC_SMI))
 		reg16 |= (3 << 0); // Periodic SMI every 8s
-	if (config->c5_enable)
+	if (southbridge_support_c5())
 		reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */
 	pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16);
 
 	/* Set exit timings for C5/C6. */
-	if (config->c5_enable) {
+	if (southbridge_support_c5()) {
 		reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING);
 		reg8 &= ~((7 << 3) | (7 << 0));
-		if (config->c6_enable)
+		if (southbridge_support_c6())
 			reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#,
 							95-102us DPRSTP# to STP_CPU# */
 		else