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mb/intel/adlrvp: Enable CPU PCIe RP 2 

Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression)
causes regression in NVMe boot on ADL-P RVP boards.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59392
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Meera Ravindranath 2021-11-17 18:11:14 +05:30 committed by Subrata Banik
parent d58599dcb8
commit 98e827ea74
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/intel/adlrvp/devicetree.cb
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@ -83,6 +83,12 @@ chip soc/intel/alderlake
.clk_src = 0, .clk_src = 0,
}" }"
# Enable CPU PCIE RP 2 using CLK 3
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_req = 3,
.clk_src = 3,
}"
# Enable CPU PCIE RP 3 using CLK 4 # Enable CPU PCIE RP 3 using CLK 4
register "cpu_pcie_rp[CPU_RP(3)]" = "{ register "cpu_pcie_rp[CPU_RP(3)]" = "{
.clk_req = 4, .clk_req = 4,