Update to Asrock E350m1 for AMD F14 C0

This updates the E350m1 Agesa wrapper code to fix an
issue with AmdLateRunApTask.  It now passes the function
parameter through to the Agesa routine.  There is also
a change to the platform_cfg.h file that makes the
definition of BIOS_SIZE dependent on whether or not
it was defined earlier.

Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/139
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

src/mainboard/asrock/e350m1/BiosCallOuts.c

@@ -377,7 +377,7 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
   AGESA_STATUS        Status;
 
-  Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
+  Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
   return Status;
 }
 

src/mainboard/asrock/e350m1/agesawrapper.c

@@ -435,42 +435,6 @@ UINT32
 agesawrapper_amdinitlate (
   VOID
   )
-{
-  AGESA_STATUS Status;
-  AMD_INTERFACE_PARAMS AmdParamStruct = {0};
-  AMD_LATE_PARAMS *AmdLateParams;
-
-  return 0; // this causes bad ACPI SSDT, need to debug
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdCreateStruct (&AmdParamStruct);
-  AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
-  Status = AmdInitLate (AmdLateParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  DmiTable    = AmdLateParams->DmiTable;
-  AcpiPstate  = AmdLateParams->AcpiPState;
-  AcpiSrat    = AmdLateParams->AcpiSrat;
-  AcpiSlit    = AmdLateParams->AcpiSlit;
-
-  AcpiWheaMce = AmdLateParams->AcpiWheaMce;
-  AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
-  AcpiAlib    = AmdLateParams->AcpiAlib;
-
-  AmdReleaseStruct (&AmdParamStruct);
-  return (UINT32)Status;
-}
-
-UINT32 
-agesawrapper_amdlaterunaptask (
-  UINT32 Data, 
-  VOID *ConfigPtr
-  )
 {
   AGESA_STATUS Status;
   AMD_LATE_PARAMS AmdLateParams;
@@ -485,7 +449,7 @@ agesawrapper_amdlaterunaptask (
   AmdLateParams.StdHeader.Func = 0;
   AmdLateParams.StdHeader.ImageBasePtr = 0;
 
-  Status = AmdLateRunApTask (&AmdLateParams);
+  Status = AmdInitLate (&AmdLateParams);
   if (Status != AGESA_SUCCESS) {
     agesawrapper_amdreadeventlog();
     ASSERT(Status == AGESA_SUCCESS);
@@ -503,6 +467,38 @@ agesawrapper_amdlaterunaptask (
   return (UINT32)Status;
 }
 
+UINT32 
+agesawrapper_amdlaterunaptask (
+  UINT32 Func, 
+  UINT32 Data, 
+  VOID *ConfigPtr
+  )
+{
+  AGESA_STATUS Status;
+  AP_EXE_PARAMS ApExeParams;
+
+  LibAmdMemFill (&ApExeParams,
+                 0,
+                 sizeof (AP_EXE_PARAMS),
+                 &(ApExeParams.StdHeader));
+
+  ApExeParams.StdHeader.AltImageBasePtr = 0;
+  ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  ApExeParams.StdHeader.Func = 0;
+  ApExeParams.StdHeader.ImageBasePtr = 0;
+  ApExeParams.StdHeader.ImageBasePtr = 0;
+  ApExeParams.FunctionNumber = Func;
+  ApExeParams.RelatedDataBlock = ConfigPtr;
+
+  Status = AmdLateRunApTask (&ApExeParams);
+  if (Status != AGESA_SUCCESS) {
+    agesawrapper_amdreadeventlog();
+    ASSERT(Status == AGESA_SUCCESS);
+  }
+
+  return (UINT32)Status;
+}
+
 UINT32 
 agesawrapper_amdreadeventlog (
   VOID

src/mainboard/asrock/e350m1/agesawrapper.h

@@ -86,6 +86,7 @@ UINT32 agesawrapper_amdinitmid (void);
 UINT32 agesawrapper_amdreadeventlog (void);
 UINT32 agesawrapper_amdinitmmio (void);
 UINT32 agesawrapper_amdinitcpuio (void);
+UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 void *agesawrapper_getlateinitptr (int pick);
 
 #endif

src/mainboard/asrock/e350m1/platform_cfg.h

@@ -36,14 +36,16 @@
  * bigger than 1M you have to set the ROM size outside CIMx module and
  * before AGESA module get call.
  */
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#ifndef BIOS_SIZE
+  #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
 	#define BIOS_SIZE BIOS_SIZE_1M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+  #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
 	#define BIOS_SIZE BIOS_SIZE_2M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+  #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
 	#define BIOS_SIZE BIOS_SIZE_4M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+  #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
 	#define BIOS_SIZE BIOS_SIZE_8M
+  #endif
 #endif
 
 /**
@@ -56,7 +58,7 @@
 
 /**
  * @def SB_HPET_TIMER
- * @breif
+ * @brief
  *  0 - Disable hpet
  *  1 - Enable  hpet
  */
@@ -79,7 +81,7 @@
 
 /**
  * @def PCI_CLOCK_CTRL
- * @breif bit[0-4] used for PCI Slots Clock Control,
+ * @brief bit[0-4] used for PCI Slots Clock Control,
  *   0 - disable
  *   1 - enable
  *  PCI SLOT 0 define at BIT0
@@ -92,26 +94,26 @@
 
 /**
  * @def SATA_CONTROLLER
- * @breif INCHIP Sata Controller
+ * @brief INCHIP Sata Controller
  */
 #define SATA_CONTROLLER		CIMX_OPTION_ENABLED
 
 /**
  * @def SATA_MODE
- * @breif INCHIP Sata Controller Mode
+ * @brief INCHIP Sata Controller Mode
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
 #define SATA_MODE			NATIVE_IDE_MODE
 
 /**
- * @breif INCHIP Sata IDE Controller Mode
+ * @brief INCHIP Sata IDE Controller Mode
  */
 #define IDE_LEGACY_MODE			0
 #define IDE_NATIVE_MODE			1
 
 /**
  * @def SATA_IDE_MODE
- * @breif INCHIP Sata IDE Controller Mode
+ * @brief INCHIP Sata IDE Controller Mode
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
 #define SATA_IDE_MODE			IDE_LEGACY_MODE
@@ -155,7 +157,7 @@
 #define AZALIA_ENABLE			2
 
 /**
- * @breif INCHIP HDA controller
+ * @brief INCHIP HDA controller
  */
 #define AZALIA_CONTROLLER		AZALIA_AUTO