nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK

This adds a file i82801gx/bootblock_gcc.c since other targets that
don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled
bootblock.c.

Tested on Foxconn D41S.

Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/cpu/intel/socket_FCBGA559/Kconfig

@@ -21,4 +21,11 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x4000
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x2000
+	help
+	  The amount of anticipated stack usage in CAR by bootblock and
+	  other stages.
+
 endif

src/cpu/intel/socket_FCBGA559/Makefile.inc

@@ -8,7 +8,9 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
+bootblock-y += ../car/non-evict/cache_as_ram.S
+
 postcar-y += ../car/non-evict/exit_car.S
 
 romstage-y += ../car/romstage.c

src/mainboard/foxconn/d41s/Makefile.inc

@@ -1,2 +1,4 @@
+romstage-y += early_init.c
+bootblock-y += early_init.c
 ramstage-y += cstates.c
 romstage-y += gpio.c

src/mainboard/foxconn/d41s/early_init.c

@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <northbridge/intel/pineview/pineview.h>
@@ -23,7 +24,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1)
 
-void mb_enable_lpc(void)
+void bootblock_mainboard_early_init(void)
 {
 	/* Disable Serial IRQ */
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);

src/mainboard/intel/d510mo/Makefile.inc

@@ -1,2 +1,4 @@
+bootblock-y += early_init.c
+romstage-y += early_init.c
 ramstage-y += cstates.c
 romstage-y += gpio.c

src/mainboard/intel/d510mo/early_init.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <northbridge/intel/pineview/pineview.h>
@@ -23,7 +24,7 @@
 #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
 #define SUPERIO_DEV PNP_DEV(0x4e, 0)
 
-void mb_enable_lpc(void)
+void bootblock_mainboard_early_init(void)
 {
 	/* Disable Serial IRQ */
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);

src/northbridge/intel/pineview/Kconfig

@@ -33,6 +33,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select SMM_TSEG
 	select PARALLEL_MP
 	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+	select C_ENVIRONMENT_BOOTBLOCK
 
 config BOOTBLOCK_NORTHBRIDGE_INIT
 	string

src/northbridge/intel/pineview/Makefile.inc

@@ -16,6 +16,8 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y)
 
+bootblock-y += bootblock.c
+
 ramstage-y += ram_calc.c
 ramstage-y += northbridge.c
 ramstage-y += gma.c

src/northbridge/intel/pineview/bootblock.c

@@ -12,11 +12,13 @@
  */
 
 #include <device/pci_ops.h>
-#define PCIEXBAR 0x60
+#include <cpu/intel/car/bootblock.h>
+#include "pineview.h"
+
 #define MMCONF_256_BUSSES 16
 #define ENABLE 1
 
-static void bootblock_northbridge_init(void)
+void bootblock_early_northbridge_init(void)
 {
 	pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
 		CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);

src/northbridge/intel/pineview/pineview.h

@@ -236,7 +236,6 @@ u32 decode_igd_gtt_size(const u32 gsm);
 u8 decode_pciebar(u32 *const base, u32 *const len);
 
 /* Mainboard romstage callback functions */
-void mb_enable_lpc(void);
 void get_mb_spd_addrmap(u8 *spd_addr_map);
 void mb_pirq_setup(void); /* optional */
 

src/northbridge/intel/pineview/romstage.c

@@ -57,20 +57,12 @@ void mainboard_romstage_entry(unsigned long bist)
 	if (bist == 0)
 		enable_lapic();
 
-	/* Disable watchdog timer */
-	RCBA32(GCS) = RCBA32(GCS) | 0x20;
-
 	/* Enable GPIOs */
 	pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
 	pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
 
 	setup_pch_gpios(&mainboard_gpio_map);
 
-	mb_enable_lpc(); // nm10_enable_lpc
-
-	/* Initialize console device(s) */
-	console_init();
-
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 

src/southbridge/intel/i82801gx/Makefile.inc

@@ -15,6 +15,8 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
 
+bootblock-y += bootblock_gcc.c
+
 ramstage-y += i82801gx.c
 ramstage-y += ac97.c
 ramstage-y += azalia.c

src/southbridge/intel/i82801gx/bootblock_gcc.c

@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_ops.h>
+#include <cpu/intel/car/bootblock.h>
+#include "i82801gx.h"
+
+static void enable_spi_prefetch(void)
+{
+	u8 reg8;
+	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+
+	reg8 = pci_read_config8(dev, BIOS_CNTL);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	pci_write_config8(dev, BIOS_CNTL, reg8);
+}
+
+void bootblock_early_southbridge_init(void)
+{
+	enable_spi_prefetch();
+
+	/* Enable RCBA */
+	pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
+	pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+
+	/* Enable upper 128bytes of CMOS */
+	RCBA32(0x3400) = (1 << 2);
+
+	/* Disable watchdog timer */
+	RCBA32(GCS) = RCBA32(GCS) | 0x20;
+}