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coreboot-kgpe-d16
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add support for AMD Serenade mainboard, why we have phantom devices here? 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo 2004-06-15 23:55:55 +00:00
parent 6ae2ac3739
commit 99efe80122
2 changed files with 16 additions and 6 deletions
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9
src/mainboard/amd/quartet/mainboard.c
View File

@ -1,4 +1,3 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@ -10,7 +9,6 @@
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1, 2, 3,
@ -28,6 +26,11 @@ static struct device_operations mainboard_operations = {
static void enumerate(struct chip *chip)
{
struct chip *child;
if (chip->control && chip->control->name) {
printk_debug("Enumerating: %s\n", chip->control->name);
}
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
@ -35,8 +38,8 @@ static void enumerate(struct chip *chip)
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_amd_quartet_control = {
.enumerate = enumerate,
.name = "AMD Quartet mainboard ",
};

11
src/mainboard/amd/solo/auto.c
View File

@ -102,20 +102,25 @@ static void main(void)
.channel1 = {0, 0, 0, 0},
}
};
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
distinguish_cpu_resets();
if (!boot_cpu()) {
print_err("This LinuxBIOS image is built for UP only.\n");
stop_this_cpu();
}
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
@ -123,20 +128,22 @@ static void main(void)
print_info("ht reset -\r\n");
soft_reset();
}
#if 0
print_pci_devices();
#endif
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
memreset_setup();
sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
#if 0
dump_pci_devices();
#endif
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 2));
#endif