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vc/intel/fsp/mtl: Add tCCD_L_WR to MemInfoHob as per FSP v3064 

This patch updates the Memory Hob Info data structure as per FSP
v3064 source code change.

BUG=b:273894357
TEST=Able to see `smbios type 17` table while booting google/rex.

Without this patch:
    [DEBUG] 0 DIMM found

With this patch:
    [DEBUG] 8 DIMM found

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3885fa7143cecc0b56e20278b69951c548ac451b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73755
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2023-03-16 15:28:06 +05:30
parent 0533867a08
commit 9a035ede17
1 changed files with 1 additions and 0 deletions
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1
src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h
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@ -192,6 +192,7 @@ typedef struct {
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group.
} MRC_CH_TIMING; } MRC_CH_TIMING;
typedef struct { typedef struct {