soc/amd/stoneyridge/fch: change sb prefix of sb_clk_output_48Mhz to fch

Stoneyridge has an integrated FCH and no south bridge, so change the sb
prefix to fch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/amd/padmelon/bootblock/bootblock.c

@@ -31,7 +31,7 @@ static void enable_serial(unsigned int base_port, unsigned int io_enable)
 
 void bootblock_mainboard_early_init(void)
 {
-	sb_clk_output_48Mhz(2);
+	fch_clk_output_48Mhz(2);
 	/*
 	 * UARTs enabled by default at reset, just need RTS, CTS
 	 * and access to the IO address.

src/soc/amd/stoneyridge/include/soc/southbridge.h

@@ -219,7 +219,7 @@ void fch_init(void *chip_info);
 void fch_final(void *chip_info);
 
 void enable_aoac_devices(void);
-void sb_clk_output_48Mhz(u32 osc);
+void fch_clk_output_48Mhz(u32 osc);
 void sb_read_mode(u32 mode);
 void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
 

src/soc/amd/stoneyridge/southbridge.c

@@ -204,7 +204,7 @@ static void sb_lpc_decode(void)
 	lpc_enable_decode(tmp);
 }
 
-void sb_clk_output_48Mhz(u32 osc)
+void fch_clk_output_48Mhz(u32 osc)
 {
 	u32 ctrl;