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soc/intel/common/block: Move gspi common functions into block/gspi 

This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/gspi.

BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.

Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2018-05-08 20:08:49 +05:30
parent c4986eb7f4
commit 9ab6d92e96
9 changed files with 86 additions and 194 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
src/soc/intel/apollolake/gspi.c
View File

@ -14,51 +14,18 @@
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <intelblocks/gspi.h>
#include <intelblocks/spi.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include "chip.h"
const struct gspi_cfg *gspi_get_soc_cfg(void)
{
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
return &common_config->gspi[0];
}
uintptr_t gspi_get_soc_early_base(void)
{
return EARLY_GSPI_BASE_ADDRESS;
}
/*
* SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
* the bus # accordingly when referring to SPI / GSPI bus numbers.
*/
#define GSPI_TO_SPI_BUS(x) (x)
#define SPI_TO_GSPI_BUS(x) ((x) - 1)
int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
{
if (spi_bus == 0)
return -1;
if (SPI_TO_GSPI_BUS(spi_bus) >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
return -1;
*gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
return 0;
}
int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
{
if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
return -1;
return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
switch (gspi_bus) {
case 0:
return PCH_DEVFN_SPI0;
case 1:
return PCH_DEVFN_SPI1;
case 2:
return PCH_DEVFN_SPI2;
}
return -1;
}

15
src/soc/intel/apollolake/spi.c
View File

@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
* Copyright 2017 Intel Corporation
* Copyright 2018 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -30,16 +30,3 @@ int spi_soc_devfn_to_bus(unsigned int devfn)
}
return -1;
}
int spi_soc_bus_to_devfn(unsigned int bus)
{
switch (bus) {
case 0:
return PCH_DEVFN_SPI0;
case 1:
return PCH_DEVFN_SPI1;
case 2:
return PCH_DEVFN_SPI2;
}
return -1;
}

51
src/soc/intel/cannonlake/gspi.c
View File

@ -14,51 +14,18 @@
* GNU General Public License for more details.
*/
#include <assert.h>
#include <device/device.h>
#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
#include <intelblocks/spi.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include "chip.h"
const struct gspi_cfg *gspi_get_soc_cfg(void)
{
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
return &common_config->gspi[0];
}
uintptr_t gspi_get_soc_early_base(void)
{
return EARLY_GSPI_BASE_ADDRESS;
}
/*
* SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
* the bus # accordingly when referring to SPI / GSPI bus numbers.
*/
#define GSPI_TO_SPI_BUS(x) ((x) + 1)
#define SPI_TO_GSPI_BUS(x) ((x) - 1)
int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
{
if (spi_bus == 0)
return -1;
*gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
return -1;
return 0;
}
int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
{
if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
return -1;
return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
switch (gspi_bus) {
case 0:
return PCH_DEVFN_GSPI0;
case 1:
return PCH_DEVFN_GSPI1;
case 2:
return PCH_DEVFN_GSPI2;
}
return -1;
}

15
src/soc/intel/cannonlake/spi.c
View File

@ -32,18 +32,3 @@ int spi_soc_devfn_to_bus(unsigned int devfn)
}
return -1;
}
int spi_soc_bus_to_devfn(unsigned int bus)
{
switch (bus) {
case 0:
return PCH_DEVFN_SPI;
case 1:
return PCH_DEVFN_GSPI0;
case 2:
return PCH_DEVFN_GSPI1;
case 3:
return PCH_DEVFN_GSPI2;
}
return -1;
}

64
src/soc/intel/common/block/gspi/gspi.c
View File

@ -23,7 +23,11 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
#include <intelblocks/spi.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <string.h>
#include <timer.h>
@ -109,6 +113,21 @@
#define GSPI_DATA_BIT_LENGTH (8)
#define GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)
/* Get base address for early init of GSPI controllers. */
static uintptr_t gspi_get_early_base(void)
{
return EARLY_GSPI_BASE_ADDRESS;
}
/* Get gspi_config array from devicetree. Returns NULL in case of error. */
static const struct gspi_cfg *gspi_get_cfg(void)
{
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
return &common_config->gspi[0];
}
#if defined(__SIMPLE_DEVICE__)
static uintptr_t gspi_get_base_addr(int devfn,
@ -131,7 +150,7 @@ void gspi_early_bar_init(void)
{
unsigned int gspi_bus;
const unsigned int gspi_max = CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX;
const struct gspi_cfg *cfg = gspi_get_soc_cfg();
const struct gspi_cfg *cfg = gspi_get_cfg();
int devfn;
uintptr_t gspi_base_addr;
@ -142,7 +161,7 @@ void gspi_early_bar_init(void)
return;
}
gspi_base_addr = gspi_get_soc_early_base();
gspi_base_addr = gspi_get_early_base();
if (!gspi_base_addr) {
printk(BIOS_ERR, "%s: GSPI base address provided is NULL!\n",
__func__);
@ -174,6 +193,41 @@ static void gspi_set_base_addr(int devfn, struct device *dev, uintptr_t base)
#endif
static int gspi_read_bus_range(unsigned int *start, unsigned int *end)
{
size_t i;
const struct spi_ctrlr_buses *desc;
for (i = 0; i < spi_ctrlr_bus_map_count; i++) {
desc = &spi_ctrlr_bus_map[i];
if (desc->ctrlr != &gspi_ctrlr)
continue;
*start = desc->bus_start;
*end = desc->bus_end;
return 0;
}
return -1;
}
static int gspi_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
{
unsigned int start;
unsigned int end;
int ret;
ret = gspi_read_bus_range(&start, &end);
if (ret != 0 || (spi_bus < start) || (spi_bus > end))
return -1;
*gspi_bus = spi_bus - start;
return 0;
}
static uintptr_t gspi_calc_base_addr(unsigned int gspi_bus)
{
uintptr_t bus_base, gspi_base_addr;
@ -191,7 +245,7 @@ static uintptr_t gspi_calc_base_addr(unsigned int gspi_bus)
if (bus_base)
return bus_base;
gspi_base_addr = gspi_get_soc_early_base();
gspi_base_addr = gspi_get_early_base();
if (!gspi_base_addr)
return 0;
@ -203,7 +257,7 @@ static uintptr_t gspi_calc_base_addr(unsigned int gspi_bus)
static uint32_t gspi_get_bus_clk_mhz(unsigned int gspi_bus)
{
const struct gspi_cfg *cfg = gspi_get_soc_cfg();
const struct gspi_cfg *cfg = gspi_get_cfg();
if (!cfg)
return 0;
return cfg[gspi_bus].speed_mhz;
@ -249,7 +303,7 @@ static int gspi_ctrlr_params_init(struct gspi_ctrlr_params *p,
{
memset(p, 0, sizeof(*p));
if (gspi_soc_spi_to_gspi_bus(spi_bus, &p->gspi_bus)) {
if (gspi_spi_to_gspi_bus(spi_bus, &p->gspi_bus)) {
printk(BIOS_ERR, "%s: No GSPI bus available for SPI bus %u.\n",
__func__, spi_bus);
return -1;

14
src/soc/intel/common/block/include/intelblocks/gspi.h
View File

@ -33,20 +33,6 @@ struct gspi_cfg {
void gspi_early_bar_init(void);
/* SoC-callbacks */
/* Get gspi_config array from SoC. Returns NULL in case of error. */
const struct gspi_cfg *gspi_get_soc_cfg(void);
/* Get base address for early init of GSPI controllers. */
uintptr_t gspi_get_soc_early_base(void);
/*
* Map given SPI bus number to GSPI bus number.
* Return value:
* 0 = success
* -1 = error
*/
int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus);
/*
* Map given GSPI bus number to devfn.
* Return value:

6
src/soc/intel/common/block/include/intelblocks/spi.h
View File

@ -28,10 +28,4 @@
*/
int spi_soc_devfn_to_bus(unsigned int devfn);
/* Function to convert input bus number to device function
* Input: Bus number
* Output: -1 translate to Error, >=0 is function number
*/
int spi_soc_bus_to_devfn(unsigned int bus);
#endif /* SOC_INTEL_COMMON_BLOCK_SPI_H */

51
src/soc/intel/skylake/gspi.c
View File

@ -13,51 +13,16 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <assert.h>
#include <device/device.h>
#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
#include <intelblocks/spi.h>
#include <soc/iomap.h>
#include "chip.h"
const struct gspi_cfg *gspi_get_soc_cfg(void)
{
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
return &common_config->gspi[0];
}
uintptr_t gspi_get_soc_early_base(void)
{
return EARLY_GSPI_BASE_ADDRESS;
}
/*
* SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
* the bus # accordingly when referring to SPI / GSPI bus numbers.
*/
#define GSPI_TO_SPI_BUS(x) (x + 1)
#define SPI_TO_GSPI_BUS(x) (x - 1)
int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
{
if (spi_bus == 0)
return -1;
*gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
return -1;
return 0;
}
#include <soc/pci_devs.h>
int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
{
if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
return -1;
return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
switch (gspi_bus) {
case 0:
return PCH_DEVFN_GSPI0;
case 1:
return PCH_DEVFN_GSPI1;
}
return -1;
}

13
src/soc/intel/skylake/spi.c
View File

@ -30,16 +30,3 @@ int spi_soc_devfn_to_bus(unsigned int devfn)
}
return -1;
}
int spi_soc_bus_to_devfn(unsigned int bus)
{
switch (bus) {
case 0:
return PCH_DEVFN_SPI;
case 1:
return PCH_DEVFN_GSPI0;
case 2:
return PCH_DEVFN_GSPI1;
}
return -1;
}