stoneyridge: Enable legacy IO

Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to
function correctly.

BUG=b:110817463
TEST=ran firmware_CorruptFwSigB on grunt

Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/amd/stoneyridge/include/soc/southbridge.h

@@ -34,6 +34,7 @@
 /* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
 #define PM_DECODE_EN			0x00
 #define   CF9_IO_EN			BIT(1)
+#define   LEGACY_IO_EN			BIT(0)
 #define PM_ISA_CONTROL			0x04
 #define   MMIO_EN			BIT(1)
 #define PM_PCI_CTRL			0x08

src/soc/amd/stoneyridge/southbridge.c

@@ -375,6 +375,13 @@ static void sb_enable_cf9_io(void)
 	pm_write32(PM_DECODE_EN, reg | CF9_IO_EN);
 }
 
+static void sb_enable_legacy_io(void)
+{
+	uint32_t reg = pm_read32(PM_DECODE_EN);
+
+	pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN);
+}
+
 void sb_clk_output_48Mhz(void)
 {
 	u32 ctrl;
@@ -550,6 +557,7 @@ void bootblock_fch_early_init(void)
 	sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
 	sb_acpi_mmio_decode();
 	sb_enable_cf9_io();
+	sb_enable_legacy_io();
 	enable_aoac_devices();
 }