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soc/intel/tgl: correct wrong gpio GPI enable register base offset 

Reference: Intel doc# 631120-001.

Change-Id: Iaf3a1b7bc38a1b30f8cc901bd6496e77f2d92cfd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner 2021-09-15 16:40:35 +02:00 committed by Patrick Georgi
parent 46ef536212
commit 9abeb9c062
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/tigerlake/include/soc/gpio_defs.h
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@ -289,7 +289,7 @@
#define GPE_DW_MASK 0xfff00 #define GPE_DW_MASK 0xfff00
#define HOSTSW_OWN_REG_0 0xb0 #define HOSTSW_OWN_REG_0 0xb0
#define GPI_INT_STS_0 0x100 #define GPI_INT_STS_0 0x100
#define GPI_INT_EN_0 0x110 #define GPI_INT_EN_0 0x120
#define GPI_SMI_STS_0 0x180 #define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1A0 #define GPI_SMI_EN_0 0x1A0
#define GPI_NMI_STS_0 0x1c0 #define GPI_NMI_STS_0 0x1c0