GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Clean up fidvid files using indent. 

Remove some special print statements.

In general, make them easier to compare.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2010-04-08 15:09:53 +00:00
parent 4839e2c495
commit 9b43afde39
33 changed files with 347 additions and 356 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

227
src/cpu/amd/model_10xxx/fidvid.c
View File

@ -17,41 +17,39 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if FAM10_SET_FIDVID == 1
#if SET_FIDVID == 1
#include "../../../northbridge/amd/amdht/AsPsDefs.h"
#define FAM10_SET_FIDVID_DEBUG 1
#define SET_FIDVID_DEBUG 1
// if we are tight of CAR stack, disable it
#define FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
static inline void print_debug_fv(const char *str, u32 val)
{
#if FAM10_SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x\n", str, val);
#if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif
}
static inline void print_debug_fv_8(const char *str, u8 val)
{
#if FAM10_SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%02x\n", str, val);
#if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif
}
static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
{
#if FAM10_SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif
}
struct fidvid_st {
u32 common_fid;
};
static void enable_fid_change(u8 fid)
{
u32 dword;
@ -61,24 +59,24 @@ static void enable_fid_change(u8 fid)
nodes = get_nodes();
for(i = 0; i < nodes; i++) {
dev = NODE_PCI(i,3);
for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 3);
dword = pci_read_config32(dev, 0xd4);
dword &= ~0x1F;
dword |= (u32) fid & 0x1F;
dword |= 1 << 5; // enable
pci_write_config32(dev, 0xd4, dword);
printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, dword);
printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
dword);
}
}
static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
{
u8 pviModeFlag;
u8 highVoltageVid, lowVoltageVid, bValue;
u16 minimumSlamTime;
u16 vSlamTimes[7]={1000,2000,3000,4000,6000,10000,20000}; /* Reg settings scaled by 100 */
u16 vSlamTimes[7] = { 1000, 2000, 3000, 4000, 6000, 10000, 20000 }; /* Reg settings scaled by 100 */
u32 dtemp;
msr_t msr;
@ -94,12 +92,10 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
* decimals.
*/
/* Determine if this is a PVI or SVI system */
dtemp = pci_read_config32(dev, 0xA0);
if( dtemp & PVI_MODE )
if (dtemp & PVI_MODE)
pviModeFlag = 1;
else
pviModeFlag = 0;
@ -113,7 +109,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
*/
if (pviModeFlag) {
bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
if( highVoltageVid > bValue )
if (highVoltageVid > bValue)
highVoltageVid = bValue;
}
@ -130,7 +126,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
*/
if (pviModeFlag) {
bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
if( lowVoltageVid > bValue )
if (lowVoltageVid > bValue)
lowVoltageVid = bValue;
}
@ -139,13 +135,13 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
bValue = (u8) (dtemp & BIT_MASK_7);
/* Use the VID with the lowest voltage (higher VID) */
if( lowVoltageVid < bValue )
if (lowVoltageVid < bValue)
lowVoltageVid = bValue;
/* If Vids are 7Dh - 7Fh, force 7Ch to keep calculations linear */
if (lowVoltageVid > 0x7C) {
lowVoltageVid = 0x7C;
if(highVoltageVid > 0x7C)
if (highVoltageVid > 0x7C)
highVoltageVid = 0x7C;
}
@ -161,8 +157,8 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
* Note that if we don't find a value, we
* will fall through to a value of 7
*/
for(bValue=0; bValue < 7; bValue++) {
if(minimumSlamTime <= vSlamTimes[bValue])
for (bValue = 0; bValue < 7; bValue++) {
if (minimumSlamTime <= vSlamTimes[bValue])
break;
}
@ -173,7 +169,6 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
pci_write_config32(dev, 0xd8, dtemp);
}
static void prep_fid_change(void)
{
u32 dword, dtemp;
@ -185,9 +180,9 @@ static void prep_fid_change(void)
nodes = get_nodes();
for(i = 0; i < nodes; i++) {
for (i = 0; i < nodes; i++) {
printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
dev = NODE_PCI(i,3);
dev = NODE_PCI(i, 3);
dword = pci_read_config32(dev, 0xd8);
dword &= VSRAMP_MASK;
@ -214,20 +209,18 @@ static void prep_fid_change(void)
*/
dword = pci_read_config32(dev, 0xd4);
dword &= CPTC0_MASK;
dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 |
LNK_PLL_LOCK; /* per BKDG */
dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | LNK_PLL_LOCK; /* per BKDG */
pci_write_config32(dev, 0xd4, dword);
} else {
dword = pci_read_config32(dev, 0xd4);
dword &= CPTC0_MASK;
/* get number of cores for PowerStepUp & PowerStepDown in server
1 core - 400nS - 0000b
2 cores - 200nS - 0010b
3 cores - 133nS -> 100nS - 0011b
4 cores - 100nS - 0011b
*/
switch(get_core_num_in_bsp(i))
{
1 core - 400nS - 0000b
2 cores - 200nS - 0010b
3 cores - 133nS -> 100nS - 0011b
4 cores - 100nS - 0011b
*/
switch (get_core_num_in_bsp(i)) {
case 0:
dword |= PW_STP_UP400 | PW_STP_DN400;
break;
@ -248,12 +241,12 @@ static void prep_fid_change(void)
/* check PVI/SVI */
dword = pci_read_config32(dev, 0xA0);
if(dword & PVI_MODE) { /* PVI */
if (dword & PVI_MODE) { /* PVI */
/* set slamVidMode to 0 for PVI */
dword &= VID_SLAM_OFF | PLLLOCK_OFF;
dword |= PLLLOCK_DFT_L;
pci_write_config32(dev, 0xA0, dword);
} else { /* SVI */
} else { /* SVI */
/* set slamVidMode to 1 for SVI */
dword &= PLLLOCK_OFF;
dword |= PLLLOCK_DFT_L | VID_SLAM_ON;
@ -264,7 +257,7 @@ static void prep_fid_change(void)
/* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */
dword = pci_read_config32(dev, 0xD8);
if( dtemp & DUAL_VDD_BIT)
if (dtemp & DUAL_VDD_BIT)
dword |= PWR_PLN_ON;
else
dword &= PWR_PLN_OFF;
@ -275,7 +268,7 @@ static void prep_fid_change(void)
* function setFidVidRegs()
*/
dword = pci_read_config32(dev, 0xDc);
dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
pci_write_config32(dev, 0xdc, dword);
/* Rev B settings - FIXME: support other revs. */
@ -313,20 +306,18 @@ static void UpdateSinglePlaneNbVid(void)
nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT;
cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT;
if( nbVid != cpuVid ) {
if(nbVid > cpuVid)
if (nbVid != cpuVid) {
if (nbVid > cpuVid)
nbVid = cpuVid;
msr.lo = msr.lo & PS_BOTH_VID_OFF;
msr.lo = msr.lo | (u32)((nbVid) << PS_NB_VID_SHFT);
msr.lo = msr.lo | (u32)((nbVid) << PS_CPU_VID_SHFT);
msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT);
msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT);
wrmsr(PS_REG_BASE + i, msr);
}
}
}
static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid)
{
msr_t msr;
@ -343,7 +334,7 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid)
*/
msr = rdmsr(0xc0010071);
startup_pstate = (msr.hi >> (32-32)) & 0x07;
startup_pstate = (msr.hi >> (32 - 32)) & 0x07;
/* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0.
* Then transition to P1 for corex and P0 for core0.
@ -379,8 +370,7 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid)
}
}
static void coreDelay (void)
static void coreDelay(void)
{
u32 saved;
u32 hi, lo, msr;
@ -390,23 +380,22 @@ static void coreDelay (void)
This seems like a hack to me...
It would be nice to have a central delay function. */
cycles = 8000 << 3; /* x8 (number of 1.25ns ticks) */
cycles = 8000 << 3; /* x8 (number of 1.25ns ticks) */
msr = 0x10; /* TSC */
msr = 0x10; /* TSC */
_RDMSR(msr, &lo, &hi);
saved = lo;
do {
_RDMSR(msr, &lo, &hi);
} while (lo - saved < cycles );
} while (lo - saved < cycles);
}
static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
{
u32 currentVid, dtemp;
msr_t msr;
u8 vsTimecode;
u16 timeTable[8]={10, 20, 30, 40, 60, 100, 200, 500};
u16 timeTable[8] = { 10, 20, 30, 40, 60, 100, 200, 500 };
int vsTime;
/* This function steps or slam the Nb VID to the target VID.
@ -416,7 +405,7 @@ static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
/* get the current VID */
msr = rdmsr(0xC0010071);
if(isNb)
if (isNb)
currentVid = (msr.lo >> NB_VID_POS) & BIT_MASK_7;
else
currentVid = (msr.lo >> CPU_VID_POS) & BIT_MASK_7;
@ -426,11 +415,11 @@ static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
/* check PVI/SPI */
dtemp = pci_read_config32(dev, 0xA0);
if (dtemp & PVI_MODE) { /* PVI, step VID */
if (dtemp & PVI_MODE) { /* PVI, step VID */
if (currentVid < targetVid) {
while (currentVid < targetVid) {
currentVid++;
if(isNb)
if (isNb)
msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS);
else
msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS);
@ -438,17 +427,17 @@ static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
/* read F3xD8[VSRampTime] */
dtemp = pci_read_config32(dev, 0xD8);
vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7);
vsTime = (int) timeTable[vsTimecode];
vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
vsTime = (int)timeTable[vsTimecode];
do {
coreDelay();
vsTime -=40;
} while(vsTime > 0);
vsTime -= 40;
} while (vsTime > 0);
}
} else if (currentVid > targetVid) {
while (currentVid > targetVid) {
currentVid--;
if(isNb)
if (isNb)
msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS);
else
msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS);
@ -456,16 +445,16 @@ static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
/* read F3xD8[VSRampTime] */
dtemp = pci_read_config32(dev, 0xD8);
vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7);
vsTime = (int) timeTable[vsTimecode];
vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
vsTime = (int)timeTable[vsTimecode];
do {
coreDelay();
vsTime -=40;
} while(vsTime > 0);
vsTime -= 40;
} while (vsTime > 0);
}
}
} else { /* SVI, slam VID */
if(isNb)
if (isNb)
msr.lo = (msr.lo & NB_VID_MASK_OFF) | (targetVid << NB_VID_POS);
else
msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (targetVid << CPU_VID_POS);
@ -473,12 +462,12 @@ static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
/* read F3xD8[VSRampTime] */
dtemp = pci_read_config32(dev, 0xD8);
vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7);
vsTime = (int) timeTable[vsTimecode];
vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
vsTime = (int)timeTable[vsTimecode];
do {
coreDelay();
vsTime -=40;
} while(vsTime > 0);
vsTime -= 40;
} while (vsTime > 0);
}
}
@ -505,13 +494,13 @@ static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
nodes = get_nodes();
nb_cof_vid_update = 0;
for (i = 0; i < nodes; i++) {
if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) {
if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
nb_cof_vid_update = 1;
break;
}
}
dev = NODE_PCI(nodeid,3);
dev = NODE_PCI(nodeid, 3);
pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
reg1fc = pci_read_config32(dev, 0x1FC);
@ -537,7 +526,7 @@ static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
}
send = (nb_cof_vid_update << 16) | (fid_max << 8);
send |= (apicid << 24); // ap apicid
send |= (apicid << 24); // ap apicid
// Send signal to BSP about this AP max fid
// This also indicates this AP is ready for warm reset (if required).
@ -553,51 +542,51 @@ static u32 calc_common_fid(u32 fid_packed, u32 fid_packed_new)
fidmax_new = (fid_packed_new >> 8) & 0xFF;
if(fidmax > fidmax_new) {
if (fidmax > fidmax_new) {
fidmax = fidmax_new;
}
fid_packed &= 0xFF << 16;
fid_packed |= (fidmax << 8);
fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update
fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update
return fid_packed;
}
static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp )
static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
{
u32 readback = 0;
u32 timeout = 1;
u32 readback = 0;
u32 timeout = 1;
struct fidvid_st *fvp = gp;
int loop;
struct fidvid_st *fvp = gp;
int loop;
print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
loop = 100000;
while(--loop > 0) {
if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) continue;
if((readback & 0x3f) == 1) {
timeout = 0;
break; //target ap is in stage 1
}
loop = 100000;
while (--loop > 0) {
if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
continue;
if ((readback & 0x3f) == 1) {
timeout = 0;
break; /* target ap is in stage 1 */
}
}
if(timeout) {
print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid);
return;
}
if (timeout) {
printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
__func__, ap_apicid);
return;
}
print_debug_fv("\treadback = ", readback);
print_debug_fv("\treadback = ", readback);
fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
}
static void updateSviPsNbVidAfterWR(u32 newNbVid)
{
msr_t msr;
@ -607,7 +596,7 @@ static void updateSviPsNbVidAfterWR(u32 newNbVid)
* for SVI mode.
*/
for( i = 0; i < 5; i++) {
for (i = 0; i < 5; i++) {
msr = rdmsr(0xC0010064 + i);
if ((msr.hi >> 31) & 1) { /* PstateEn? */
msr.lo &= ~(0x7F << 25);
@ -632,13 +621,13 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll)
*/
/* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
for( i = 0; i < 5; i++) {
for (i = 0; i < 5; i++) {
msr = rdmsr(0xC0010064 + i);
/* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */
if ((((msr.lo >> 22) & 1) == 0) || NbVidUpdatedAll) {
msr.lo &= ~(0x7F << 25);
msr.lo |= (newNbVid & 0x7F) << 25;
wrmsr (0xC0010064 + i, msr);
wrmsr(0xC0010064 + i, msr);
}
}
@ -651,13 +640,12 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll)
msr.lo = StartupPstate;
wrmsr(0xC0010062, msr);
/* Wait for StartupPstate to set.*/
/* Wait for StartupPstate to set. */
do {
msr = rdmsr(0xC0010063);
} while (msr.lo != StartupPstate);
}
static void set_p0(void)
{
msr_t msr;
@ -673,8 +661,8 @@ static void set_p0(void)
} while (msr.lo != 0);
}
static void finalPstateChange (void) {
static void finalPstateChange(void)
{
/* Enble P0 on all cores for best performance.
* Linux can slow them down later if need be.
* It is safe since they will be in C1 halt
@ -683,7 +671,6 @@ static void finalPstateChange (void) {
set_p0();
}
static void init_fidvid_stage2(u32 apicid, u32 nodeid)
{
msr_t msr;
@ -703,13 +690,13 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid)
nodes = get_nodes();
nb_cof_vid_update = 0;
for (i = 0; i < nodes; i++) {
if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) {
if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
nb_cof_vid_update = 1;
break;
}
}
dev = NODE_PCI(nodeid,3);
dev = NODE_PCI(nodeid, 3);
pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
reg1fc = pci_read_config32(dev, 0x1FC);
nbvid = (reg1fc >> 7) & 0x7F;
@ -724,7 +711,7 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid)
nbvid = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F);
updateSviPsNbVidAfterWR(nbvid);
}
} else { /* !nb_cof_vid_update */
} else { /* !nb_cof_vid_update */
if (pvimode)
UpdateSinglePlaneNbVid();
}
@ -742,7 +729,7 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid)
}
#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
struct ap_apicid_st {
u32 num;
// it could use 256 bytes for 64 node quad core system
@ -761,7 +748,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp)
static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
{
#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
struct ap_apicid_st ap_apicidx;
u32 i;
#endif
@ -785,7 +772,7 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
/* If any node has nb_cof_vid_update set all nodes need an update. */
nb_cof_vid_update = 0;
for (i = 0; i < nodes; i++) {
if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) {
if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
nb_cof_vid_update = 1;
break;
}
@ -810,29 +797,29 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
/* fid setup is handled by the BSP at the end. */
} else { /* ! nb_cof_vid_update */
} else { /* ! nb_cof_vid_update */
/* Use max values */
if (pvimode)
UpdateSinglePlaneNbVid();
}
fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8) ;
fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8);
print_debug_fv("BSP fid = ", fv.common_fid);
#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && FAM10_SET_FIDVID_CORE0_ONLY == 0
#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && SET_FIDVID_CORE0_ONLY == 0
/* For all APs (We know the APIC ID of all APs even when the APIC ID
is lifted) remote read from AP LAPIC_MSG_REG about max fid.
Then calculate the common max fid that can be used for all
APs and BSP */
ap_apicidx.num = 0;
for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
for_each_ap(bsp_apicid, SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
for(i = 0; i < ap_apicidx.num; i++) {
for (i = 0; i < ap_apicidx.num; i++) {
init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
}
#else
for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
#endif
print_debug_fv("common_fid = ", fv.common_fid);
@ -846,6 +833,6 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
return 1;
}
return 0; // No FID/VID changes. Don't reset
return 0; // No FID/VID changes. Don't reset
}
#endif

16
src/cpu/amd/model_10xxx/init_cpus.c
View File

@ -20,14 +20,14 @@
#include "defaults.h"
//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef FAM10_SET_FIDVID
#define FAM10_SET_FIDVID 1
#ifndef SET_FIDVID
#define SET_FIDVID 1
#endif
#ifndef FAM10_SET_FIDVID_CORE0_ONLY
#ifndef SET_FIDVID_CORE0_ONLY
/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
Need to do every AP to set common FID/VID*/
#define FAM10_SET_FIDVID_CORE0_ONLY 0
#define SET_FIDVID_CORE0_ONLY 0
#endif
static void print_initcpu8 (const char *strval, u8 val)
@ -217,7 +217,7 @@ static int lapic_remote_read(int apicid, int reg, u32 *pvalue)
#define LAPIC_MSG_REG 0x380
#if FAM10_SET_FIDVID == 1
#if SET_FIDVID == 1
static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
#endif
@ -398,8 +398,8 @@ static u32 init_cpus(u32 cpu_init_detectedx)
cpuSetAMDMSR();
#if FAM10_SET_FIDVID == 1
#if (CONFIG_LOGICAL_CPUS == 1) && (FAM10_SET_FIDVID_CORE0_ONLY == 1)
#if SET_FIDVID == 1
#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1)
// Run on all AP for proper FID/VID setup.
if(id.coreid == 0 ) // only need set fid for core0
#endif
@ -994,7 +994,7 @@ void finalize_node_setup(struct sys_info *sysinfo)
cpuSetAMDPCI(i);
}
#if FAM10_SET_FIDVID == 1
#if SET_FIDVID == 1
// Prep each node for FID/VID setup.
prep_fid_change();
#endif

302
src/cpu/amd/model_fxx/fidvid.c
View File

@ -1,10 +1,10 @@
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
#define K8_SET_FIDVID_DEBUG 0
#define SET_FIDVID_DEBUG 0
#define K8_SET_FIDVID_ONE_BY_ONE 1
#define SET_FIDVID_ONE_BY_ONE 1
#define K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
#ifndef SB_VFSMAF
#define SB_VFSMAF 1
@ -12,78 +12,77 @@
#define FX_SUPPORT 1
static inline void print_debug_fv(const char *str, unsigned val)
static inline void print_debug_fv(const char *str, u32 val)
{
#if K8_SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x\n", str, val);
#if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif
}
static inline void print_debug_fv_8(const char *str, unsigned val)
static inline void print_debug_fv_8(const char *str, u8 val)
{
#if K8_SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%02x\n", str, val);
#if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif
}
static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2)
static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
{
#if K8_SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif
}
static void enable_fid_change(void)
{
uint32_t dword;
unsigned nodes;
u32 dword;
u32 nodes;
int i;
nodes = ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60) >> 4) & 7) + 1;
for (i = 0; i < nodes; i++) {
dword = pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xd8);
dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 3), 0xd8);
dword &= 0x8ff00000;
dword |= (2 << 28) | (0x02710);
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0xd8, dword);
pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0xd8, dword);
dword = 0x04e2a707;
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0xd4, dword);
pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0xd4, dword);
/* disable the DRAM interface at first, it will be enabled
* by raminit again */
dword = pci_read_config32(PCI_DEV(0, 0x18+i, 2), 0x94);
dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94);
dword |= (1 << 14);
pci_write_config32(PCI_DEV(0, 0x18+i, 2), 0x94, dword);
pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword);
dword = 0x23070700; /* enable FID/VID change */
// dword = 0x00070000; /* enable FID/VID change */
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword);
dword = 0x23070700; /* enable FID/VID change */
// dword = 0x00070000; /* enable FID/VID change */
pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0x80, dword);
#if CONFIG_HAVE_ACPI_RESUME
dword = 0x21132113;
#else
dword = 0x00132113;
#endif
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x84, dword);
pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0x84, dword);
}
}
#if K8_SET_FIDVID_ONE_BY_ONE == 0
#if SET_FIDVID_ONE_BY_ONE == 0
static unsigned set_fidvid_without_init(unsigned fidvid)
{
msr_t msr;
uint32_t vid;
uint32_t fid;
u32 vid;
u32 fid;
fid = (fidvid >> 8) & 0x3f;
vid = (fidvid >> 16) & 0x3f;
/* set new FID/VID */
msr.hi = 1;
msr.lo = (vid<<8) | fid;
msr.lo = (vid << 8) | fid;
wrmsr(0xc0010041, msr);
return fidvid;
}
@ -117,12 +116,12 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
};
msr_t msr;
uint32_t vid_new;
uint32_t fid_new;
uint32_t vid_max;
uint32_t fid_max;
uint32_t vid_cur;
uint32_t fid_cur;
u32 vid_new;
u32 fid_new;
u32 vid_max;
u32 fid_max;
u32 vid_cur;
u32 fid_cur;
unsigned apicidx;
int step_limit;
@ -131,7 +130,9 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
apicidx = lapicid();
if (apicid != apicidx) {
printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\n", apicid, apicidx);
printk(BIOS_ERR,
"wrong apicid, we want change %x, but it is %x\n",
apicid, apicidx);
return fidvid;
}
@ -146,14 +147,14 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
if ((vid_cur == vid_new) && (fid_cur == fid_new))
return fidvid;
vid_max = (msr.hi >> (48-32)) & 0x3f;
fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */
vid_max = (msr.hi >> (48 - 32)) & 0x3f;
fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */
#if FX_SUPPORT
if (fid_max >= ((25 - 4) * 2)) { /* FX max fid is 5G */
fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* max FID is min fid + 1G */
if (fid_max >= ((25-4) * 2)) {
fid_max = (10-4) * 2; /* hard set to 2G */
if (fid_max >= ((25 - 4) * 2)) { /* FX max fid is 5G */
fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* max FID is min fid + 1G */
if (fid_max >= ((25 - 4) * 2)) {
fid_max = (10 - 4) * 2; /* hard set to 2G */
}
}
#endif
@ -162,25 +163,24 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
/* TODO - make this more correct. Not a big deal for setting max...
* BKDG figure 11
* if TargetFID > InitialFID
* TargetVID = FinalVID - RVO
* TargetVID = FinalVID - RVO
* else
* if CurrentVID > FinalVID
* TargetVID = FinalVID - RVO
* else
* TargetVID = CurrentVIDD - RVO
* if CurrentVID > FinalVID
* TargetVID = FinalVID - RVO
* else
* TargetVID = CurrentVIDD - RVO
*/
msr.hi = 1;
msr.lo = (vid_max << 8) | (fid_cur);
#if SB_VFSMAF == 1
msr.lo |= (1 << 16); /* init changes */
msr.lo |= (1 << 16); /* init changes */
#endif
wrmsr(0xc0010041, msr);
#if SB_VFSMAF == 0
ldtstop_sb();
#endif
for (loop=0; loop < 100000; loop++){
for (loop = 0; loop < 100000; loop++) {
msr = rdmsr(0xc0010042);
if (!(msr.lo & (1 << 31)))
break;
@ -201,19 +201,20 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
* transition to target fid
*/
printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, fid_max);
printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur,
fid_max);
printk(BIOS_DEBUG, "Requested fid_new: 0x%x\n", fid_new);
step_limit = 8; /* max 8 steps just in case... */
step_limit = 8; /* max 8 steps just in case... */
while ((fid_cur != fid_new) && (step_limit--)) {
u32 fid_temp;
int step;
if (fid_cur < fid_new)
/* Force Fid steps even. step == 0 means 100MHz step */
step = ((fid_new/2) - (fid_cur/2)) * 2;
step = ((fid_new / 2) - (fid_cur / 2)) * 2;
else
step = ((fid_cur/2) - (fid_new/2)) * 2;
step = ((fid_cur / 2) - (fid_new / 2)) * 2;
/* If 200Mhz step OR past 3200 max table value */
if ((step == 2) || (fid_new >= 0x18 || fid_cur >= 0x18)) {
@ -226,23 +227,23 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
else
fid_temp = fid_cur - 2;
} else if ( step > 2) { /* If more than a 200Mhz step */
} else if (step > 2) { /* If more than a 200Mhz step */
int temp;
/* look it up in the table */
printk(BIOS_DEBUG, "FidVid table step ");
temp = next_fid_200[((fid_new/2) * 13) + (fid_cur/2)];
temp =
next_fid_200[((fid_new / 2) * 13) + (fid_cur / 2)];
if (temp > 0)
fid_temp = (temp-4) * 2; /* Table 108 */
fid_temp = (temp - 4) * 2; /* Table 108 */
else if (temp == 0)
fid_temp = fid_new;
else
break; /* table error */
break; /* table error */
} else { /* step < 2 (100MHZ) */
} else { /* step < 2 (100MHZ) */
printk(BIOS_DEBUG, "100MHZ step ");
/* The table adjust in 200MHz increments. If requested,
@ -256,41 +257,41 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
}
}
if(fid_temp > fid_max) {
printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n", fid_temp, fid_max);
if (fid_temp > fid_max) {
printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n",
fid_temp, fid_max);
break;
}
printk(BIOS_DEBUG, "fidvid: 0x%x\n", fid_temp);
/* set target fid */
msr.hi = 0x190; /* 2 us for AMD NPT Family 0Fh Processors */
msr.hi = 0x190; /* 2 us for AMD NPT Family 0Fh Processors */
msr.lo = (vid_cur << 8) | fid_temp;
#if SB_VFSMAF == 1
msr.lo |= (1 << 16); /* init changes */
msr.lo |= (1 << 16); /* init changes */
#endif
wrmsr(0xc0010041, msr);
#if SB_VFSMAF == 0
ldtstop_sb();
#endif
#if K8_SET_FIDVID_DEBUG == 1
#if SET_FIDVID_DEBUG == 1
if (showmessage) {
print_debug_fv_8("set_fidvid APICID = ", apicid);
print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo);
}
#endif
for (loop = 0; loop < 100000; loop++){
for (loop = 0; loop < 100000; loop++) {
msr = rdmsr(0xc0010042);
if (!(msr.lo & (1 << 31)))
break;
}
fid_cur = msr.lo & 0x3f;
#if K8_SET_FIDVID_DEBUG == 1
if (showmessage) {
#if SET_FIDVID_DEBUG == 1
if (showmessage) {
print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo);
}
#endif
@ -310,14 +311,14 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
msr.hi = 1;
msr.lo = (vid_new << 8) | (fid_cur);
#if SB_VFSMAF == 1
msr.lo |= (1 << 16); // init changes
msr.lo |= (1 << 16); // init changes
#endif
wrmsr(0xc0010041, msr);
#if SB_VFSMAF == 0
ldtstop_sb();
#endif
for (loop = 0; loop < 100000; loop++){
for (loop = 0; loop < 100000; loop++) {
msr = rdmsr(0xc0010042);
if (!(msr.lo & (1 << 31)))
break;
@ -328,10 +329,12 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
if (showmessage) {
if (vid_new != vid_cur) {
print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\n");
printk(BIOS_ERR, "set vid failed for apicid =%02x\n",
apicidx);
}
if (fid_new != fid_cur) {
print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\n");
printk(BIOS_ERR, "set fid failed for apicid =%02x\n",
apicidx);
}
}
@ -341,35 +344,35 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
{
uint32_t send;
uint32_t readback = 0;
u32 send;
u32 readback = 0;
unsigned timeout = 1;
msr_t msr;
uint32_t vid_cur;
uint32_t fid_cur;
uint32_t fid_max;
u32 vid_cur;
u32 fid_cur;
u32 fid_max;
int loop;
msr = rdmsr(0xc0010042);
fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */
msr = rdmsr(0xc0010042);
fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */
#if FX_SUPPORT
if (fid_max >= ((25-4) * 2)) { /* FX max fid is 5G */
fid_max = ((msr.lo>>8) & 0x3f) + 5*2; /* maxFID = minFID + 1G */
if (fid_max >= ((25-4) * 2)) {
fid_max = (10-4) * 2; // hard set to 2G
if (fid_max >= ((25 - 4) * 2)) { /* FX max fid is 5G */
fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* maxFID = minFID + 1G */
if (fid_max >= ((25 - 4) * 2)) {
fid_max = (10 - 4) * 2; // hard set to 2G
}
}
#endif
send = fid_max<<8;
send = fid_max << 8;
send |= ((msr.hi >> (48-32)) & 0x3f) << 16; /* max vid */
send |= (apicid << 24); /* ap apicid */
send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16; /* max vid */
send |= (apicid << 24); /* ap apicid */
#if K8_SET_FIDVID_ONE_BY_ONE == 1
#if SET_FIDVID_ONE_BY_ONE == 1
vid_cur = msr.hi & 0x3f;
fid_cur = msr.lo & 0x3f;
/* set to current */
/* set to current */
msr.hi = 1;
msr.lo = (vid_cur << 8) | (fid_cur);
wrmsr(0xc0010041, msr);
@ -377,52 +380,55 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
timeout = wait_cpu_state(bsp_apicid, 1);
if (timeout) {
print_initcpu8("fidvid_ap_stage1: time out while reading from BSP on ", apicid);
printk(BIOS_DEBUG, "fidvid_ap_stage1: time out while reading"
" from BSP on %02x\n", apicid);
}
/* send signal to BSP about this AP max fid and vid */
/* AP at state 1 that sent our fid and vid */
lapic_write(LAPIC_MSG_REG, send | 1);
// wait_cpu_state(bsp_apicid, 2); /* don't need we can use apicid directly */
// wait_cpu_state(bsp_apicid, 2); /* don't need we can use apicid directly */
loop = 1000000;
while (--loop > 0) {
/* remote read BSP signal that include vid/fid that need to set */
if (lapic_remote_read(bsp_apicid, LAPIC_MSG_REG, &readback)!=0)
if (lapic_remote_read(bsp_apicid, LAPIC_MSG_REG, &readback) !=
0)
continue;
if (((readback >> 24) & 0xff) == apicid)
break; /* it is this cpu turn */
break; /* it is this cpu turn */
}
if (loop > 0) {
#if K8_SET_FIDVID_ONE_BY_ONE == 1
readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP
#else
readback = set_fidvid_without_init(readback & 0xffff00); // this AP
#endif
#if SET_FIDVID_ONE_BY_ONE == 1
readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP
#else
readback = set_fidvid_without_init(readback & 0xffff00); // this AP
#endif
/* send signal to BSP that this AP fid/vid is set */
/* allow to change state2 is together with apicid */
/* AP at state that We set the requested fid/vid */
send = (apicid<<24) | (readback & 0x00ffff00);
send = (apicid << 24) | (readback & 0x00ffff00);
} else {
print_initcpu8("fidvid_ap_stage2: time out while reading from BSP on ", apicid);
printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x",
__func__, apicid);
}
lapic_write(LAPIC_MSG_REG, send | 2);
lapic_write(LAPIC_MSG_REG, send | 2);
timeout = wait_cpu_state(bsp_apicid, 3);
if (timeout) {
print_initcpu8("fidvid_ap_stage3: time out while reading from BSP on ", apicid);
printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x",
__func__, apicid);
}
}
static unsigned calc_common_fidvid(unsigned fidvid, unsigned fidvidx)
static u32 calc_common_fidvid(unsigned fidvid, unsigned fidvidx)
{
/* FIXME: need to check the change path to verify if it is reachable
* when common fid is small than 1.6G */
if ((fidvid & 0xff00) <= (fidvidx & 0xff00)) {
return fidvid;
}
else {
} else {
return fidvidx;
}
}
@ -431,10 +437,10 @@ struct fidvid_st {
unsigned common_fidvid;
};
static void init_fidvid_bsp_stage1(unsigned ap_apicid, void *gp )
static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
{
unsigned readback = 0;
unsigned timeout = 1;
u32 readback = 0;
u32 timeout = 1;
struct fidvid_st *fvp = gp;
int loop;
@ -443,19 +449,21 @@ static void init_fidvid_bsp_stage1(unsigned ap_apicid, void *gp )
loop = 1000000;
while (--loop > 0) {
if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0)
if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
continue;
if ((readback & 0xff) == 1) {
timeout = 0;
break; /* target ap is in stage 1 */
break; /* target ap is in stage 1 */
}
}
if (timeout) {
print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid);
printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
__func__, ap_apicid);
return;
}
print_debug_fv("\treadback=", readback);
print_debug_fv("\treadback = ", readback);
fvp->common_fidvid = calc_common_fidvid(fvp->common_fidvid, readback & 0xffff00);
@ -473,31 +481,31 @@ static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp)
print_debug_fv("state 2: ap_apicid=", ap_apicid);
/* all set to state2 */
lapic_write(LAPIC_MSG_REG, fvp->common_fidvid | (ap_apicid<<24) | 2);
lapic_write(LAPIC_MSG_REG, fvp->common_fidvid | (ap_apicid << 24) | 2);
loop = 1000000;
while (--loop > 0) {
if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0)
if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
continue;
if ((readback & 0xff) == 2) {
timeout = 0;
break; /* target ap is stage 2, it's FID has beed set */
break; /* target ap is stage 2, it's FID has beed set */
}
}
if (timeout) {
print_initcpu8("fidvid_bsp_stage2: time out while reading from ap ", ap_apicid);
printk(BIOS_DEBUG, "%s: time out while reading from ap %02x",
__func__, ap_apicid);
return;
}
print_debug_fv("\treadback=", readback);
}
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
struct ap_apicid_st {
unsigned num;
unsigned apicid[16]; /* 8 way dual core need 16 */
/* FIXME: 32 node quad core, may need 128 */
u32 num;
unsigned apicid[16]; /* 8 way dual core need 16 */
};
static void store_ap_apicid(unsigned ap_apicid, void *gp)
@ -511,77 +519,75 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp)
static void init_fidvid_bsp(unsigned bsp_apicid)
{
uint32_t vid_max;
uint32_t fid_max;
u32 vid_max;
u32 fid_max;
struct fidvid_st fv;
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
struct ap_apicid_st ap_apicidx;
unsigned i;
#endif
msr_t msr;
msr = rdmsr(0xc0010042);
fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */
msr = rdmsr(0xc0010042);
fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */
#if FX_SUPPORT == 1
if (fid_max >= ((25-4) * 2)) { /* FX max fid is 5G */
fid_max = ((msr.lo >> 8) & 0x3f) + 5*2; /* maxFID = minFID + 1G */
if (fid_max >= ((25-4) * 2)) {
fid_max = (10-4) * 2; /* hard set to 2G */
if (fid_max >= ((25 - 4) * 2)) { /* FX max fid is 5G */
fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* maxFID = minFID + 1G */
if (fid_max >= ((25 - 4) * 2)) {
fid_max = (10 - 4) * 2; /* hard set to 2G */
}
}
#endif
vid_max = ((msr.hi>>(48-32)) & 0x3f); //max vid
fv.common_fidvid = (fid_max << 8)|(vid_max << 16);
vid_max = ((msr.hi >> (48 - 32)) & 0x3f); //max vid
fv.common_fidvid = (fid_max << 8) | (vid_max << 16);
/* for all APs (We know the APIC ID of all APs even the APIC ID is lifted)
* remote read from AP about max fid/vid */
/* let all ap trains to state 1 */
lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 1);
lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 1);
/* calculate the common max fid/vid that could be used for
* all APs and BSP */
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
ap_apicidx.num = 0;
for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx);
for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx);
for (i = 0; i < ap_apicidx.num; i++) {
init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
}
#else
for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
#endif
#if 0
unsigned fid, vid;
/* Can we use max only? So we can only set fid in one around,
* otherwise we need to set that to max after raminit */
/* set fid vid to DQS training required */
fid = (fv.common_fidvid >> 8) & 0x3f;
fid = (fv.common_fidvid >> 8) & 0x3f;
vid = (fv.common_fidvid >> 16) & 0x3f;
if (fid > (10-4) * 2) {
fid = (10-4) * 2; // x10
if (fid > (10 - 4) * 2) {
fid = (10 - 4) * 2; // x10
}
if (vid >= 0x1f) {
vid += 4; /* unit is 12.5mV */
vid += 4; /* unit is 12.5mV */
} else {
vid += 2; /* unit is 25mV */
vid += 2; /* unit is 25mV */
}
fv.common_fidvid = (fid<<8) | (vid<<16);
fv.common_fidvid = (fid << 8) | (vid << 16);
print_debug_fv("common_fidvid=", fv.common_fidvid);
#endif
#if K8_SET_FIDVID_ONE_BY_ONE == 1
#if SET_FIDVID_ONE_BY_ONE == 1
/* set BSP fid and vid */
print_debug_fv("bsp apicid=", bsp_apicid);
fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
@ -595,15 +601,15 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
fv.common_fidvid &= 0xffff00;
/* set state 2 allow is in init_fidvid_bsp_stage2 */
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
for (i = 0; i < ap_apicidx.num; i++) {
init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv);
}
#else
for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv);
for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv);
#endif
#if K8_SET_FIDVID_ONE_BY_ONE == 0
#if SET_FIDVID_ONE_BY_ONE == 0
/* set BSP fid and vid */
print_debug_fv("bsp apicid=", bsp_apicid);
fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
@ -616,7 +622,5 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
/* here wait a while, so last ap could read pack, and stop it, don't
* call init_timer too early or just don't use init_timer */
}
#endif

16
src/cpu/amd/model_fxx/init_cpus.c
View File

@ -1,17 +1,17 @@
//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef K8_SET_FIDVID
#ifndef SET_FIDVID
#if CONFIG_K8_REV_F_SUPPORT == 0
#define K8_SET_FIDVID 0
#define SET_FIDVID 0
#else
// for rev F, need to set FID to max
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
#endif
#endif
#ifndef K8_SET_FIDVID_CORE0_ONLY
#ifndef SET_FIDVID_CORE0_ONLY
/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice*/
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#endif
static inline void print_initcpu8 (const char *strval, unsigned val)
@ -149,7 +149,7 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned *pvalue)
#define LAPIC_MSG_REG 0x380
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid);
#endif
@ -302,8 +302,8 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
if(apicid != bsp_apicid) {
unsigned timeout=1;
unsigned loop = 100;
#if K8_SET_FIDVID == 1
#if (CONFIG_LOGICAL_CPUS == 1) && (K8_SET_FIDVID_CORE0_ONLY == 1)
#if SET_FIDVID == 1
#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1)
if(id.coreid == 0 ) // only need set fid for core0
#endif
init_fidvid_ap(bsp_apicid, apicid);

2
src/mainboard/amd/dbm690t/romstage.c
View File

@ -18,7 +18,7 @@
*/
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1

2
src/mainboard/amd/mahogany/romstage.c
View File

@ -18,7 +18,7 @@
*/
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1

6
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -34,8 +34,8 @@
#define FAM10_ALLOCATE_IO_RANGE 0
//used by init_cpus and fidvid
#define FAM10_SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
#include <stdint.h>
#include <string.h>
@ -208,7 +208,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb700_early_setup();
#if FAM10_SET_FIDVID == 1
#if SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);

2
src/mainboard/amd/pistachio/romstage.c
View File

@ -18,7 +18,7 @@
*/
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1

8
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -10,9 +10,9 @@
//#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid
#define K8_SET_FIDVID 0
#define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -164,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset;
unsigned bsp_apicid = 0;
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
struct cpuid_result cpuid1;
#endif
@ -228,7 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);

6
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -34,8 +34,8 @@
#define FAM10_ALLOCATE_IO_RANGE 0
//used by init_cpus and fidvid
#define FAM10_SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
#include <stdint.h>
#include <string.h>
@ -211,7 +211,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
#if FAM10_SET_FIDVID == 1
#if SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);

2
src/mainboard/asrock/939a785gmh/romstage.c
View File

@ -19,7 +19,7 @@
*/
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1

4
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -32,10 +32,10 @@ unsigned int get_sbdn(unsigned bus);
#define QRANK_DIMM_SUPPORT 1
/* Used by init_cpus and fidvid */
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
/* If we want to wait for core1 done before DQS training, set it to 0. */
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#include <stdint.h>
#include <string.h>

4
src/mainboard/asus/m2v-mx_se/romstage.c
View File

@ -32,10 +32,10 @@ unsigned int get_sbdn(unsigned bus);
#define QRANK_DIMM_SUPPORT 1
/* Used by init_cpus and fidvid */
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
/* If we want to wait for core1 done before DQS training, set it to 0. */
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0

6
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -32,9 +32,9 @@
#endif
//used by init_cpus and fidvid
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -235,7 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr;

6
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -30,9 +30,9 @@
#endif
//used by init_cpus and fidvid
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr;

6
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -36,9 +36,9 @@
#endif
//used by init_cpus and fidvid
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -252,7 +252,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
bcm5785_early_setup();
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr;
msr=rdmsr(0xc0010042);

6
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -10,9 +10,9 @@
//#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid
#define K8_SET_FIDVID 0
#define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr;

6
src/mainboard/iwill/dk8s2/romstage.c
View File

@ -10,9 +10,9 @@
//#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid
#define K8_SET_FIDVID 0
#define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr;

6
src/mainboard/iwill/dk8x/romstage.c
View File

@ -10,9 +10,9 @@
//#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid
#define K8_SET_FIDVID 0
#define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr;

2
src/mainboard/kontron/kt690/romstage.c
View File

@ -19,7 +19,7 @@
*/
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1

6
src/mainboard/msi/ms7260/romstage.c
View File

@ -33,10 +33,10 @@
#endif
/* Used by init_cpus and fidvid. */
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
/* If we want to wait for core1 done before DQS training, set it to 0. */
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -214,7 +214,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Set up chains and store link pair for optimization later. */
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr = rdmsr(0xc0010042);
print_debug("begin msr fid, vid ");

6
src/mainboard/msi/ms9185/romstage.c
View File

@ -35,9 +35,9 @@
//#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#include <stdint.h>
#include <string.h>
@ -221,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr;

4
src/mainboard/msi/ms9282/romstage.c
View File

@ -31,9 +31,9 @@
#define QRANK_DIMM_SUPPORT 1
//used by init_cpus and fidvid
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#include <stdint.h>
#include <string.h>

6
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -30,8 +30,8 @@
#define SET_NB_CFG_54 1
#endif
#define FAM10_SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
#define DBGP_DEFAULT 7
@ -248,7 +248,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
#if FAM10_SET_FIDVID == 1
#if SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

6
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -30,9 +30,9 @@
#endif
//used by init_cpus and fidvid
#define K8_SET_FIDVID 0
#define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -236,7 +236,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr;

6
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -27,9 +27,9 @@
#endif
// used by init_cpus and fidvid
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -295,7 +295,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr;

6
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -30,9 +30,9 @@
#endif
//used by init_cpus and fidvid
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -223,7 +223,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr;

6
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -30,8 +30,8 @@
#define SET_NB_CFG_54 1
#endif
#define FAM10_SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
#include <stdint.h>
#include <string.h>
@ -235,7 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
#if FAM10_SET_FIDVID == 1
#if SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);

6
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -30,8 +30,8 @@
#define SET_NB_CFG_54 1
#endif
#define FAM10_SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
#include <stdint.h>
#include <string.h>
@ -280,7 +280,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
#if FAM10_SET_FIDVID == 1
#if SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);

2
src/mainboard/technexion/tim5690/romstage.c
View File

@ -18,7 +18,7 @@
*/
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1

2
src/mainboard/technexion/tim8690/romstage.c
View File

@ -18,7 +18,7 @@
*/
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1

6
src/mainboard/tyan/s2912/romstage.c
View File

@ -30,9 +30,9 @@
#endif
//used by init_cpus and fidvid
#define K8_SET_FIDVID 0
#define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -232,7 +232,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
#if SET_FIDVID == 1
{
msr_t msr;

6
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -30,8 +30,8 @@
#define SET_NB_CFG_54 1
#endif
#define FAM10_SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
#define DBGP_DEFAULT 7
@ -243,7 +243,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
#if FAM10_SET_FIDVID == 1
#if SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);