soc/intel/alderlake/chip.h: Use boolean type where applicable
Change-Id: If26184058536590b70bbb03209913118307ff6c5 Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76830 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Strosche
Felix Singer
parent
b470624c74
commit
9c0c8b0b64
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@ -338,17 +338,17 @@ struct soc_intel_alderlake_config {
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uint32_t gen4_dec;
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/* Enable S0iX support */
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int s0ix_enable;
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bool s0ix_enable;
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/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
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uint8_t tcss_d3_hot_disable;
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bool tcss_d3_hot_disable;
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/* Enable DPTF support */
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int dptf_enable;
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bool dptf_enable;
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/* Deep SX enable for both AC and DC */
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int deep_s3_enable_ac;
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int deep_s3_enable_dc;
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int deep_s5_enable_ac;
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int deep_s5_enable_dc;
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bool deep_s3_enable_ac;
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bool deep_s3_enable_dc;
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bool deep_s5_enable_ac;
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bool deep_s5_enable_dc;
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/* Deep Sx Configuration
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* DSX_EN_WAKE_PIN - Enable WAKE# pin
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@ -376,7 +376,7 @@ struct soc_intel_alderlake_config {
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} sagv;
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/* Rank Margin Tool. 1:Enable, 0:Disable */
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uint8_t RMT;
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bool RMT;
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/* USB related */
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struct usb2_port_config usb2_ports[16];
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@ -390,21 +390,21 @@ struct soc_intel_alderlake_config {
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/* SATA related */
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uint8_t sata_mode;
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uint8_t sata_salp_support;
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uint8_t sata_ports_enable[8];
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uint8_t sata_ports_dev_slp[8];
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bool sata_salp_support;
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bool sata_ports_enable[8];
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bool sata_ports_dev_slp[8];
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/*
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* Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
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* Default 0. Setting this to 1 disables the SATA Power Optimizer.
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*/
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uint8_t sata_pwr_optimize_disable;
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bool sata_pwr_optimize_disable;
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/*
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* SATA Port Enable Dito Config.
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* Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
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*/
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uint8_t sata_ports_enable_dito_config[8];
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bool sata_ports_enable_dito_config[8];
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/* SataPortsDmVal is the DITO multiplier. Default is 15. */
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uint8_t sata_ports_dm_val[8];
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@ -413,8 +413,8 @@ struct soc_intel_alderlake_config {
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uint16_t sata_ports_dito_val[8];
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/* Audio related */
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uint8_t pch_hda_audio_link_hda_enable;
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uint8_t pch_hda_dsp_enable;
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bool pch_hda_audio_link_hda_enable;
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bool pch_hda_dsp_enable;
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bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];
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/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
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@ -460,13 +460,14 @@ struct soc_intel_alderlake_config {
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IGD_SM_56MB = 0xFD,
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IGD_SM_60MB = 0xFE,
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} igd_dvmt50_pre_alloc;
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uint8_t skip_ext_gfx_scan;
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bool skip_ext_gfx_scan;
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/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
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uint8_t eist_enable;
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bool eist_enable;
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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bool enable_c6dram;
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/*
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* SerialIO device mode selection:
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@ -493,7 +494,7 @@ struct soc_intel_alderlake_config {
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uint8_t serial_io_gspi_cs_state[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
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/* Enable Pch iSCLK */
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uint8_t pch_isclk;
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bool pch_isclk;
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/* CNVi BT Core Enable/Disable */
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bool cnvi_bt_core;
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@ -525,7 +526,7 @@ struct soc_intel_alderlake_config {
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* 0: Use FSP default GPIO PM program,
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* 1: coreboot to override GPIO PM program
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*/
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uint8_t gpio_override_pm;
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bool gpio_override_pm;
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/*
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* GPIO PM configuration: 0 to disable, 1 to enable power gating
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@ -553,11 +554,11 @@ struct soc_intel_alderlake_config {
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/* Hybrid storage mode enable (1) / disable (0)
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* This mode makes FSP detect Optane and NVME and set PCIe lane mode
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* accordingly */
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uint8_t hybrid_storage_mode;
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bool hybrid_storage_mode;
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#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
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/* eMMC HS400 mode */
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uint8_t emmc_enable_hs400_mode;
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bool emmc_enable_hs400_mode;
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#endif
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/*
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@ -577,7 +578,7 @@ struct soc_intel_alderlake_config {
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* Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
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* Default 0. Setting this to 1 disables the DMI Power Optimizer.
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*/
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uint8_t dmi_power_optimize_disable;
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bool dmi_power_optimize_disable;
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/*
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* Used to communicate the power delivery design capability of the board. This
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@ -590,7 +591,7 @@ struct soc_intel_alderlake_config {
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* Enable(1)/Disable(0) CPU Replacement check.
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* Default 0. Setting this to 1 to check CPU replacement.
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*/
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uint8_t cpu_replacement_check;
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bool cpu_replacement_check;
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/* ISA Serial Base selection. */
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enum {
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@ -694,7 +695,7 @@ struct soc_intel_alderlake_config {
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*/
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uint8_t fivr_spread_spectrum;
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/* Enable or Disable Acoustic Noise Mitigation feature */
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uint8_t acoustic_noise_mitigation;
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bool acoustic_noise_mitigation;
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/*
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* Acoustic Noise Mitigation Range. Defines the maximum Pre-Wake
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* randomization time in micro ticks. This can be programmed only
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@ -703,7 +704,7 @@ struct soc_intel_alderlake_config {
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*/
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uint8_t PreWake;
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/* Disable Fast Slew Rate for Deep Package C States for VR domains */
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uint8_t fast_pkg_c_ramp_disable[NUM_VR_DOMAINS];
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bool fast_pkg_c_ramp_disable[NUM_VR_DOMAINS];
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/*
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* Slew Rate configuration for Deep Package C States for VR domains
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* 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values
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