soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable

SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using
a HECI message that needs to be sent before EOP. Make the option
configurable to allow soft ME disable on alderlake.

Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/soc/intel/alderlake/Kconfig

@@ -117,7 +117,6 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
-	select SOC_INTEL_CSE_SEND_EOP_EARLY
 	select SOC_INTEL_CSE_SET_EOP
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select HAVE_INTEL_COMPLIANCE_TEST_MODE
@@ -459,6 +458,9 @@ config USE_COREBOOT_MP_INIT
 
 endchoice
 
+config SOC_INTEL_CSE_SEND_EOP_EARLY
+	default y
+
 if STITCH_ME_BIN
 
 config CSE_BPDT_VERSION

src/soc/intel/common/block/cse/Kconfig

@@ -46,7 +46,7 @@ config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR
 	  to make `HECI1` device disable using private configuration register (PCR) write.
 
 config SOC_INTEL_CSE_SEND_EOP_EARLY
-	bool
+	bool "CSE send EOP early"
 	depends on SOC_INTEL_COMMON_BLOCK_CSE
 	help
 	  Use this config to send End Of Post (EOP) earlier through SoC code in order to