soc/intel/apollolake: work around full retrain constraints on warm reset
It's come to attention that apollolake doesn't support a full retrain on warm reset. Therefore force a cold reset when a full retrain is requested in the non-S5 path. BUG=b:37687843 Change-Id: If9a3de1fa8760e7bb2f06eef93a0deb9dbd3f047 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19483 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -143,6 +143,9 @@
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/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
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#define PRSTS 0x1000
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#define GEN_PMCON1 0x1020
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#define COLD_BOOT_STS (1 << 27)
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#define COLD_RESET_STS (1 << 26)
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#define WARM_RESET_STS (1 << 25)
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#define SRS (1 << 20)
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#define RPS (1 << 2)
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#define GEN_PMCON2 0x1024
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@ -31,6 +31,7 @@
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#include <fsp/api.h>
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#include <fsp/memmap.h>
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#include <fsp/util.h>
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#include <reset.h>
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#include <soc/cpu.h>
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#include <soc/flash_ctrlr.h>
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#include <soc/intel/common/mrc_cache.h>
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@ -258,10 +259,27 @@ static void fill_console_params(FSPM_UPD *mupd)
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}
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}
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static void check_full_retrain(const FSPM_UPD *mupd)
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{
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struct chipset_power_state *ps;
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if (mupd->FspmArchUpd.BootMode != FSP_BOOT_WITH_FULL_CONFIGURATION)
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return;
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ps = car_get_var_ptr(&power_state);
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if (ps->gen_pmcon1 & WARM_RESET_STS) {
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printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n");
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hard_reset();
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}
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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{
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struct region_device rdev;
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check_full_retrain(mupd);
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fill_console_params(mupd);
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mainboard_memory_init_params(mupd);
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