soc/intel/apollolake: work around full retrain constraints on warm reset

It's come to attention that apollolake doesn't support a full retrain
on warm reset. Therefore force a cold reset when a full retrain is
requested in the non-S5 path.

BUG=b:37687843

Change-Id: If9a3de1fa8760e7bb2f06eef93a0deb9dbd3f047
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19483
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/apollolake/include/soc/pm.h

@@ -143,6 +143,9 @@
 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */
 #define PRSTS			0x1000
 #define GEN_PMCON1		0x1020
+#define  COLD_BOOT_STS		(1 << 27)
+#define  COLD_RESET_STS		(1 << 26)
+#define  WARM_RESET_STS		(1 << 25)
 #define  SRS			(1 << 20)
 #define  RPS			(1 << 2)
 #define GEN_PMCON2		0x1024

src/soc/intel/apollolake/romstage.c

@@ -31,6 +31,7 @@
 #include <fsp/api.h>
 #include <fsp/memmap.h>
 #include <fsp/util.h>
+#include <reset.h>
 #include <soc/cpu.h>
 #include <soc/flash_ctrlr.h>
 #include <soc/intel/common/mrc_cache.h>
@@ -258,10 +259,27 @@ static void fill_console_params(FSPM_UPD *mupd)
 	}
 }
 
+static void check_full_retrain(const FSPM_UPD *mupd)
+{
+	struct chipset_power_state *ps;
+
+	if (mupd->FspmArchUpd.BootMode != FSP_BOOT_WITH_FULL_CONFIGURATION)
+		return;
+
+	ps = car_get_var_ptr(&power_state);
+
+	if (ps->gen_pmcon1 & WARM_RESET_STS) {
+		printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n");
+		hard_reset();
+	}
+}
+
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
 	struct region_device rdev;
 
+	check_full_retrain(mupd);
+
 	fill_console_params(mupd);
 	mainboard_memory_init_params(mupd);