This patch adds support for the AMD Norwich development platform
based on the Geode LX processor. The Norwich is the canonical Geode reference, and will server as a good basis for other Geode based platforms. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
Stefan Reinauer
parent
bc8176c552
commit
9c9083ba4a
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_PIRQ_TABLE
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object irq_tables.o
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end
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#object reset.o
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if USE_DCACHE_RAM
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#compile cache_as_ram.c to auto.inc
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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##
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## Romcc output
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##
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#makerule ./failover.E
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# depends "$(MAINBOARD)/failover.c ./romcc"
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# action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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#end
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#
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#makerule ./failover.inc
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# depends "$(MAINBOARD)/failover.c ./romcc"
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# action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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#end
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#
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#makerule ./auto.E
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# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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# action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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#end
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#makerule ./auto.inc
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# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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# action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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#end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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# mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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if USE_DCACHE_RAM
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mainboardinit cpu/amd/model_lx/cache_as_ram.inc
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mainboardinit ./cache_as_ram_auto.inc
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end
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/amd/lx
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device pci_domain 0 on
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device pci 1.0 on end # Northbridge
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device pci 1.1 on end # Graphics
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chip southbridge/amd/cs5536
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# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
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# SIRQ Mode = Active(Quiet) mode. Save power....
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
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register "lpc_serirq_enable" = "0x00001002"
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register "lpc_serirq_polarity" = "0x0000EFFD"
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register "lpc_serirq_mode" = "1"
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register "enable_gpio_int_route" = "0x0D0C0700"
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register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
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register "enable_USBP4_device" = "0" #0: host, 1:device
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register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
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register "com1_enable" = "1"
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register "com1_address" = "0x3F8"
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register "com1_irq" = "4"
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register "com2_enable" = "1"
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register "com2_address" = "0x2F8"
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register "com2_irq" = "3"
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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device pci b.0 on end # Slot 3
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device pci c.0 on end # Slot 4
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device pci d.0 on end # Slot 1
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device pci e.0 on end # Slot 2
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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# APIC cluster is late CPU init.
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device apic_cluster 0 on
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chip cpu/amd/model_lx
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device apic 0 on end
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end
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end
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end
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@ -0,0 +1,179 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HAVE_OPTION_TABLE
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uses USE_OPTION_TABLE
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uses CONFIG_ROM_PAYLOAD
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uses IRQ_SLOT_COUNT
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses LINUXBIOS_EXTRA_VERSION
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uses ARCH
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uses FALLBACK_SIZE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses _RAMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_VIDEO_MB
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 256*1024
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###
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### Build options
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###
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default CONFIG_CONSOLE_VGA=0
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default CONFIG_VIDEO_MB=8
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default CONFIG_PCI_ROM_RUN=0
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## no MP table
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##
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default HAVE_MP_TABLE=0
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=0
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## Delay timer options
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##
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default CONFIG_UDELAY_TSC=1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=6
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#object irq_tables.o
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=0
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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default FALLBACK_SIZE = 131072
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##
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## enable CACHE_AS_RAM specifics
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##
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default USE_DCACHE_RAM=1
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default DCACHE_RAM_BASE=0xc8000
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default DCACHE_RAM_SIZE=0x08000
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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default CONFIG_ROM_PAYLOAD = 1
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##
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## The default compiler
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##
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default CROSS_COMPILE=""
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## The Serial Console
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##
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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#default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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##
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### Select the linuxBIOS loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=8
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## At a maximum only compile in this level of debugging
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default MAXIMUM_CONSOLE_LOGLEVEL=8
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end
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@ -0,0 +1,92 @@
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/*
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*
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* Copyright (C) 2007 Advanced Micro Devices
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*
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*/
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/lxdef.h>
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#include <cpu/amd/geode_post_code.h>
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#include "southbridge/amd/cs5536/cs5536.h"
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#define POST_CODE(x) outb(x, 0x80)
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#define ManualConf 0 /* Do automatic strapped PLL config */
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#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
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#define PLLMSRlo 0x02000030
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#define DIMM0 0xA0
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#define DIMM1 0xA2
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#include "northbridge/amd/lx/raminit.h"
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#include "northbridge/amd/lx/pll_reset.c"
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#include "northbridge/amd/lx/raminit.c"
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#include "sdram/generic_sdram.c"
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#include "cpu/amd/model_lx/cpureginit.c"
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#include "cpu/amd/model_lx/syspreinit.c"
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static void msr_init(void)
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{
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/* Setup access to the MC for low memory. Note MC not setup yet. */
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__builtin_wrmsr(CPU_RCONF_DEFAULT, 0x10f3bf00, 0x24fffc02);
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__builtin_wrmsr(MSR_GLIU0 + 0x20, 0xfff80, 0x20000000);
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__builtin_wrmsr(MSR_GLIU0 + 0x21, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(MSR_GLIU1 + 0x20, 0xfff80, 0x20000000);
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__builtin_wrmsr(MSR_GLIU1 + 0x21, 0x80fffe0, 0x20000000);
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}
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||||
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||||
static void mb_gpio_init(void)
|
||||
{
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/* Early mainboard specific GPIO setup */
|
||||
}
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||||
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static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl [] = {
|
||||
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
msr_init();
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||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/* NOTE: must do this AFTER the early_setup!
|
||||
* it is counting on some early MSR setup
|
||||
* for cs5536
|
||||
*/
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||||
/* cs5536_disable_internal_uart disable them for now, set them up later...*/
|
||||
cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
|
||||
mb_gpio_init();
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||||
uart_init();
|
||||
console_init();
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Check all of memory */
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||||
//ram_check(0x00000000, 640*1024);
|
||||
}
|
||||
|
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@ -0,0 +1,118 @@
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/*
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices
|
||||
*
|
||||
*/
|
||||
|
||||
#define ASSEMBLY 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <arch/hlt.h>
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "cpu/x86/msr.h"
|
||||
#include <cpu/amd/lxdef.h>
|
||||
#include <cpu/amd/geode_post_code.h>
|
||||
#include "southbridge/amd/cs5536/cs5536.h"
|
||||
|
||||
#define POST_CODE(x) outb(x, 0x80)
|
||||
|
||||
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
|
||||
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#define ManualConf 0 /* Do automatic strapped PLL config */
|
||||
#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
|
||||
#define PLLMSRlo 0x02000030
|
||||
#define DIMM0 0xA0
|
||||
#define DIMM1 0xA2
|
||||
#include "northbridge/amd/lx/raminit.h"
|
||||
#include "northbridge/amd/lx/pll_reset.c"
|
||||
#include "northbridge/amd/lx/raminit.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
msr_t msr;
|
||||
/* Setup access to the cache for under 1MB. */
|
||||
msr.hi = 0x24fffc02;
|
||||
msr.lo = 0x1000A000; /* 0-A0000 write back */
|
||||
wrmsr(CPU_RCONF_DEFAULT, msr);
|
||||
|
||||
msr.hi = 0x0; /* write back */
|
||||
msr.lo = 0x0;
|
||||
wrmsr(CPU_RCONF_A0_BF, msr);
|
||||
wrmsr(CPU_RCONF_C0_DF, msr);
|
||||
wrmsr(CPU_RCONF_E0_FF, msr);
|
||||
|
||||
/* Setup access to the cache for under 640K. Note MC not setup yet. */
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU0 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU0 + 0x21, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU1 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU1 + 0x21, msr);
|
||||
|
||||
}
|
||||
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/* Early mainboard specific GPIO setup */
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
{
|
||||
POST_CODE(0x01);
|
||||
|
||||
static const struct mem_controller memctrl [] = {
|
||||
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/* NOTE: must do this AFTER the early_setup!
|
||||
* it is counting on some early MSR setup
|
||||
* for cs5536
|
||||
*/
|
||||
/* cs5536_disable_internal_uart disable them for now, set them up later...*/
|
||||
cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
|
||||
mb_gpio_init();
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Check all of memory */
|
||||
/*ram_check(0x00000000, 640*1024);*/
|
||||
|
||||
/* Memory is setup. Return to cache_as_ram.inc and continue to boot */
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices
|
||||
*
|
||||
|
||||
*/
|
||||
|
||||
extern struct chip_operations mainboard_amd_norwich_ops;
|
||||
|
||||
struct mainboard_amd_norwich_config {
|
||||
int nothing;
|
||||
};
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
440 1 e 0 dcon_present
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
static void print_debug_pci_dev(unsigned dev)
|
||||
{
|
||||
print_debug("PCI: ");
|
||||
print_debug_hex8((dev >> 16) & 0xff);
|
||||
print_debug_char(':');
|
||||
print_debug_hex8((dev >> 11) & 0x1f);
|
||||
print_debug_char('.');
|
||||
print_debug_hex8((dev >> 8) & 7);
|
||||
}
|
||||
|
||||
static void print_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_pci_device(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
|
||||
for(i = 0; i <= 255; i++) {
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
print_debug_char(' ');
|
||||
print_debug_hex8(val);
|
||||
if ((i & 0x0f) == 0x0f) {
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
dump_pci_device(dev);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include "arch/romcc_io.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
#if 0
|
||||
/* This is the primary cpu how should I boot? */
|
||||
if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
asm volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
cpu_reset:
|
||||
asm volatile ("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
fallback_image:
|
||||
#endif
|
||||
return bist;
|
||||
}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include "../../../southbridge/amd/cs5536/cs5536.h"
|
||||
|
||||
/* Platform IRQs */
|
||||
#define PIRQA 11
|
||||
#define PIRQB 5
|
||||
#define PIRQC 10
|
||||
#define PIRQD 10
|
||||
|
||||
/* Map */
|
||||
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
|
||||
|
||||
/* Link */
|
||||
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
|
||||
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
|
||||
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
|
||||
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x0F<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x100B, /* Vendor */
|
||||
0x002B, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00,(0x01<<3)|0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
|
||||
{0x00,(0x0F<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
|
||||
{0x00,(0x0D<<3)|0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
|
||||
{0x00,(0x0E<<3)|0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
|
||||
{0x00,(0x0B<<3)|0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */
|
||||
{0x00,(0x0C<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr){
|
||||
int i, j, k, num_entries;
|
||||
unsigned char pirq[4];
|
||||
uint16_t chipset_irq_map;
|
||||
uint32_t pciAddr, pirtable_end;
|
||||
struct irq_routing_table *pirq_tbl;
|
||||
|
||||
pirtable_end = copy_pirq_routing_table(addr);
|
||||
|
||||
/* Set up chipset IRQ steering */
|
||||
pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
|
||||
chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
|
||||
printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map);
|
||||
outl(pciAddr & ~3, 0xCF8);
|
||||
outl(chipset_irq_map, 0xCFC);
|
||||
|
||||
pirq_tbl = (struct irq_routing_table *)(addr);
|
||||
num_entries = (pirq_tbl->size - 32)/16;
|
||||
|
||||
/* Set PCI IRQs */
|
||||
for (i=0; i < num_entries; i++){
|
||||
printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
|
||||
for (j = 0; j < 4; j++){
|
||||
printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap);
|
||||
for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */
|
||||
pirq[j] = k;
|
||||
printk_debug("PIRQ: %d\n", k);
|
||||
}
|
||||
pci_assign_irqs(pirq_tbl->slots[i].bus,
|
||||
pirq_tbl->slots[i].devfn >> 3, pirq); /* bus, device, slots IRQs for {A,B,C,D} */
|
||||
}
|
||||
|
||||
/* put the PIR table in memory and checksum */
|
||||
return pirtable_end;
|
||||
}
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <arch/io.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/lxdef.h>
|
||||
#include <device/pci_def.h>
|
||||
#include "../../../southbridge/amd/cs5536/cs5536.h"
|
||||
#include "chip.h"
|
||||
|
||||
/* Print the platform configuration - do before PCI init or it will not work right */
|
||||
void print_conf(void) {
|
||||
#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
|
||||
int i;
|
||||
unsigned long iol;
|
||||
msr_t msr;
|
||||
|
||||
int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG,
|
||||
CPU_DM_CONFIG0, CPU_RCONF_DEFAULT,
|
||||
CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF,
|
||||
CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
|
||||
};
|
||||
|
||||
int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
|
||||
GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
|
||||
GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW,
|
||||
GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
|
||||
GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
|
||||
GLIU0_GLD_MSR_COH, GL_END
|
||||
};
|
||||
|
||||
int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
|
||||
MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10,
|
||||
GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
|
||||
GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
|
||||
GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
|
||||
GLIU1_GLD_MSR_COH, GL_END
|
||||
};
|
||||
|
||||
int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
|
||||
CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
|
||||
};
|
||||
|
||||
int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT,
|
||||
MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
|
||||
};
|
||||
|
||||
int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF,
|
||||
GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE,
|
||||
GL_END
|
||||
};
|
||||
|
||||
int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4,
|
||||
MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
|
||||
MDD_DMA_SHAD9, GL_END
|
||||
};
|
||||
|
||||
|
||||
printk_debug("---------- CPU ------------\n");
|
||||
|
||||
for(i = 0; cpu_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(cpu_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 0 ------------\n");
|
||||
|
||||
for(i = 0; gliu0_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu0_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 1 ------------\n");
|
||||
|
||||
for(i = 0; gliu1_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu1_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- RCONF ------------\n");
|
||||
|
||||
for(i = 0; rconf_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(rconf_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- VARIA ------------\n");
|
||||
msr = rdmsr(0x51300010);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo);
|
||||
|
||||
msr = rdmsr(0x51400015);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo);
|
||||
|
||||
printk_debug("---------- DIVIL IRQ ------------\n");
|
||||
msr = rdmsr(MDD_IRQM_YLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_YHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo);
|
||||
|
||||
|
||||
printk_debug("---------- PCI ------------\n");
|
||||
|
||||
for(i = 0; pci_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(pci_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- LPC/UART DMA ------------\n");
|
||||
|
||||
for(i = 0; dma_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(dma_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- CS5536 ------------\n");
|
||||
|
||||
for(i = 0; cs5536_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(cs5536_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
|
||||
iol = inl(GPIOL_EVENTS_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
|
||||
iol = inl(GPIOL_INPUT_INVERT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
|
||||
iol = inl(GPIO_MAPPER_X);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, iol);
|
||||
#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
|
||||
}
|
||||
|
||||
static void init(struct device *dev) {
|
||||
printk_debug("Norwich ENTER %s\n", __FUNCTION__);
|
||||
printk_debug("Norwich EXIT %s\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
dev->ops->init = init;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_amd_norwich_ops = {
|
||||
CHIP_NAME("AMD Norwich Mainboard")
|
||||
.enable_dev = enable_dev,
|
||||
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
# Config file for the AMD Geode LX/5536 Norwich Platform
|
||||
|
||||
target norwich
|
||||
mainboard amd/norwich
|
||||
|
||||
#HACK to get the right tsc support
|
||||
option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
# leave 36k for vsa
|
||||
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
|
||||
option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
|
||||
|
||||
option ROM_SIZE=512*1024-36*1024
|
||||
#option ROM_SIZE=256*1024-36*1024
|
||||
option FALLBACK_SIZE=ROM_SIZE
|
||||
|
||||
option DEFAULT_CONSOLE_LOGLEVEL = 11
|
||||
option MAXIMUM_CONSOLE_LOGLEVEL = 11
|
||||
#option DEFAULT_CONSOLE_LOGLEVEL = 4
|
||||
#option MAXIMUM_CONSOLE_LOGLEVEL = 4
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
option ROM_IMAGE_SIZE=64*1024
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
|
||||
payload ../payload.elf
|
||||
end
|
||||
|
||||
buildrom ./norwich.rom ROM_SIZE "fallback"
|
||||
Loading…
Reference in New Issue