soc/amd/picasso: Fix the typo in GPIO define

Change-Id: I8c9eed5d0e320b02382c24304a44e51e89eb6ac5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/mainboard/amd/mandolin/emmc_gpio.c

@@ -6,7 +6,7 @@
 /* eMMC controller driving either an SD card or eMMC device. */
 static const struct soc_amd_gpio emmc_gpios[] = {
 	PAD_NF(GPIO_21,  EMMC_CMD,	PULL_UP),
-	PAD_NF(GPIO_22,  EMMC_PRW_CTRL,	PULL_UP),
+	PAD_NF(GPIO_22,  EMMC_PWR_CTRL,	PULL_UP),
 	PAD_NF(GPIO_68,  EMMC_CD,	PULL_UP),
 	PAD_NF(GPIO_70,  EMMC_CLK,	PULL_NONE),
 	PAD_NF(GPIO_104, EMMC_DATA0,	PULL_UP),

src/mainboard/amd/mandolin/variants/cereme/early_gpio.c

@@ -13,7 +13,7 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
 	/* not USB_OC2_L */
 	PAD_GPI(GPIO_18, PULL_UP),
 	/* SDIO eMMC power control */
-	PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE),
+	PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE),
 	/* PCIe Reset 0 */
 	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
 	/* PCIe Reset 1 */

src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c

@@ -17,7 +17,7 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
 	/* not USB_OC2_L */
 	PAD_GPI(GPIO_18, PULL_UP),
 	/* SDIO eMMC power control */
-	PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE),
+	PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE),
 	/* PCIe SSD power enable */
 	PAD_GPO(GPIO_23, HIGH),
 	/* PCIe Reset to DP0, DP1, J2105, TP, FP */

src/soc/amd/picasso/include/soc/gpio.h

@@ -146,7 +146,7 @@
 #define GPIO_21_IOMUX_EMMC_CMD 1
 #define GPIO_21_IOMUX_GPIOxx 2
 #define GPIO_22_IOMUX_LPC_PME_L 0
-#define GPIO_22_IOMUX_EMMC_PRW_CTRL 1
+#define GPIO_22_IOMUX_EMMC_PWR_CTRL 1
 #define GPIO_22_IOMUX_GPIOxx 2
 #define GPIO_23_IOMUX_AC_PRES 0
 #define GPIO_23_IOMUX_SGPIO_LOAD 1