soc/intel/broadwell/pch: Use Lynxpoint GPIO code
This allows dropping `gpio.c` from Broadwell. Change-Id: I6b34e11f849cdf01e402fe79d078711af94e1ec0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50081 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -4,9 +4,9 @@ ramstage-y += adsp.c
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romstage-y += early_pch.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += finalize.c
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ramstage-y += gpio.c
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romstage-y += gpio.c
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smm-y += gpio.c
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ramstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
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romstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
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smm-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
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ramstage-y += hda.c
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ramstage-y += iobp.c
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romstage-y += iobp.c
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@ -1,133 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/iomap.h>
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#include <soc/pm.h>
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#include <southbridge/intel/lynxpoint/lp_gpio.h>
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/*
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* This function will return a number that indicates which PIRQ
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* this GPIO maps to. If this is not a PIRQ capable GPIO then
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* it will return -1. The GPIO to PIRQ mapping is not linear.
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*/
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static int gpio_to_pirq(int gpio)
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{
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switch (gpio) {
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case 8: return 0; /* PIRQI */
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case 9: return 1; /* PIRQJ */
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case 10: return 2; /* PIRQK */
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case 13: return 3; /* PIRQL */
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case 14: return 4; /* PIRQM */
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case 45: return 5; /* PIRQN */
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case 46: return 6; /* PIRQO */
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case 47: return 7; /* PIRQP */
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case 48: return 8; /* PIRQQ */
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case 49: return 9; /* PIRQR */
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case 50: return 10; /* PIRQS */
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case 51: return 11; /* PIRQT */
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case 52: return 12; /* PIRQU */
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case 53: return 13; /* PIRQV */
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case 54: return 14; /* PIRQW */
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case 55: return 15; /* PIRQX */
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default: return -1;
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};
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}
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void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[])
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{
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const struct pch_lp_gpio_map *config;
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u32 owner[3] = {0};
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u32 route[3] = {0};
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u32 irqen[3] = {0};
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u32 reset[3] = {0};
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u32 blink = 0;
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u16 pirq2apic = 0;
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int set, bit, gpio = 0;
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for (config = map; config->conf0 != GPIO_LIST_END; config++, gpio++) {
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if (gpio > MAX_GPIO_NUMBER)
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break;
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/* Setup Configuration registers 1 and 2 */
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outl(config->conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio));
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outl(config->conf1, GPIO_BASE_ADDRESS + GPIO_CONFIG1(gpio));
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/* Determine set and bit based on GPIO number */
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set = gpio >> 5;
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bit = gpio % 32;
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/* Apply settings to set specific bits */
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owner[set] |= config->owner << bit;
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route[set] |= config->route << bit;
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irqen[set] |= config->irqen << bit;
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reset[set] |= config->reset << bit;
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if (set == 0)
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blink |= config->blink << bit;
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/* PIRQ to IO-APIC map */
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if (config->pirq == GPIO_PIRQ_APIC_ROUTE) {
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set = gpio_to_pirq(gpio);
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if (set >= 0)
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pirq2apic |= 1 << set;
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}
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}
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for (set = 0; set <= 2; set++) {
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outl(owner[set], GPIO_BASE_ADDRESS + GPIO_OWNER(set));
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outl(route[set], GPIO_BASE_ADDRESS + GPIO_ROUTE(set));
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outl(irqen[set], GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set));
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outl(reset[set], GPIO_BASE_ADDRESS + GPIO_RESET(set));
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}
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outl(blink, GPIO_BASE_ADDRESS + GPIO_BLINK);
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outl(pirq2apic, GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN);
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}
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int get_gpio(int gpio_num)
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{
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if (gpio_num > MAX_GPIO_NUMBER)
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return 0;
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return !!(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
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}
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/*
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* get a number comprised of multiple GPIO values. gpio_num_array points to
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* the array of gpio pin numbers to scan, terminated by -1.
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*/
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unsigned int get_gpios(const int *gpio_num_array)
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{
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int gpio;
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unsigned int bitmask = 1;
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unsigned int vector = 0;
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while (bitmask &&
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((gpio = *gpio_num_array++) != -1)) {
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if (get_gpio(gpio))
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vector |= bitmask;
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bitmask <<= 1;
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}
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return vector;
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}
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void set_gpio(int gpio_num, int value)
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{
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u32 conf0;
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if (gpio_num > MAX_GPIO_NUMBER)
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return;
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conf0 = inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num));
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conf0 &= ~GPO_LEVEL_MASK;
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conf0 |= value << GPO_LEVEL_SHIFT;
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outl(conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num));
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}
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int gpio_is_native(int gpio_num)
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{
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return !(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & 1);
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}
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