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google/kahlee: Fix GPIO ASL 

Use a single define and set the CROS GPIO ASL device to match the
Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN
field in the GPIO ASL. This addresses the TEST indicated below.

BUG=b:65597554
BRANCH=none
TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030.

Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marc Jones 2017-09-20 17:09:19 -06:00 committed by Aaron Durbin
parent 469c01ebd2
commit 9cffe25ce0
3 changed files with 14 additions and 9 deletions
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9
src/mainboard/google/kahlee/acpi/carrizo_fch.asl
View File

@ -13,6 +13,8 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <soc/gpio.h>
Device (AAHB) Device (AAHB)
{ {
Name (_HID, "AAHB0000") Name (_HID, "AAHB0000")
@ -30,9 +32,10 @@ Device (AAHB)
Device (GPIO) Device (GPIO)
{ {
Name (_HID, "AMD0030") Name (_HID, GPIO_DEVICE_NAME)
Name (_CID, "AMD0030") Name (_CID, GPIO_DEVICE_NAME)
Name(_UID, 0) Name (_UID, 0)
Name (_DDN, GPIO_DEVICE_DESC)
Name (_CRS, ResourceTemplate() Name (_CRS, ResourceTemplate()
{ {

6
src/mainboard/google/kahlee/chromeos.c
View File

@ -21,7 +21,7 @@
#include <gpio.h> #include <gpio.h>
/* SPI Write protect */ /* SPI Write protect */
#define CROS_WP_GPIO GPIO_122 #define CROS_WP_GPIO GPIO_142
void fill_lb_gpios(struct lb_gpios *gpios) void fill_lb_gpios(struct lb_gpios *gpios)
{ {
@ -40,8 +40,8 @@ int get_write_protect_state(void)
} }
static const struct cros_gpio cros_gpios[] = { static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_WP_GPIO, GPIO_DEVICE_NAME),
}; };
void mainboard_chromeos_acpi_generate(void) void mainboard_chromeos_acpi_generate(void)

8
src/soc/amd/stoneyridge/include/soc/gpio.h
View File

@ -16,11 +16,13 @@
#ifndef __STONEYRIDGE_GPIO_H__ #ifndef __STONEYRIDGE_GPIO_H__
#define __STONEYRIDGE_GPIO_H__ #define __STONEYRIDGE_GPIO_H__
#define GPIO_DEVICE_NAME "AMD0030"
#define GPIO_DEVICE_DESC "GPIO Controller"
#ifndef __ACPI__
#include <soc/amd/common/amd_defs.h> #include <soc/amd/common/amd_defs.h>
#include <types.h> #include <types.h>
#define CROS_GPIO_DEVICE_NAME "AmdKern"
#define GPIO_PIN_STS (1 << 16) #define GPIO_PIN_STS (1 << 16)
#define GPIO_PULLUP_ENABLE (1 << 20) #define GPIO_PULLUP_ENABLE (1 << 20)
#define GPIO_PULLDOWN_ENABLE (1 << 21) #define GPIO_PULLDOWN_ENABLE (1 << 21)
@ -132,5 +134,5 @@
#define GPIO_148 148 #define GPIO_148 148
typedef uint32_t gpio_t; typedef uint32_t gpio_t;
#endif /* __ACPI__ */
#endif /* __STONEYRIDGE_GPIO_H__ */ #endif /* __STONEYRIDGE_GPIO_H__ */