GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/apollolake: Allow USB2 eye pattern configuration in devicetree 

This code allows people to override the usb2 eye pattern
UPD settings for boards.

BUG=chrome-os-partner:61031
BRANCH=None
TEST=Usb2 function ok and make sure fsp upd is overridden

Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/18060
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kane Chen 2017-01-11 12:53:58 +08:00 committed by Aaron Durbin
parent e7056a82e0
commit 9d490daf8d
3 changed files with 70 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
src/soc/intel/apollolake/chip.c
View File

@ -436,6 +436,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
{
FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
static struct soc_intel_apollolake_config *cfg;
uint8_t port;
/* Load VBT before devicetree-specific config. */
silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
@ -491,6 +492,37 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* Bios config lockdown Audio clk and power gate */
silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
/* USB2 eye diagram settings per port */
for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0)
silconfig->PortUsb20PerPortTxPeHalf[port] =
cfg->usb2eye[port].Usb20PerPortTxPeHalf;
if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0)
silconfig->PortUsb20PerPortPeTxiSet[port] =
cfg->usb2eye[port].Usb20PerPortPeTxiSet;
if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0)
silconfig->PortUsb20PerPortTxiSet[port] =
cfg->usb2eye[port].Usb20PerPortTxiSet;
if (cfg->usb2eye[port].Usb20HsSkewSel != 0)
silconfig->PortUsb20HsSkewSel[port] =
cfg->usb2eye[port].Usb20HsSkewSel;
if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0)
silconfig->PortUsb20IUsbTxEmphasisEn[port] =
cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
if (cfg->usb2eye[port].Usb20PerPortRXISet != 0)
silconfig->PortUsb20PerPortRXISet[port] =
cfg->usb2eye[port].Usb20PerPortRXISet;
if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0)
silconfig->PortUsb20HsNpreDrvSel[port] =
cfg->usb2eye[port].Usb20HsNpreDrvSel;
}
}
struct chip_operations soc_intel_apollolake_ops = {

5
src/soc/intel/apollolake/chip.h
View File

@ -24,6 +24,7 @@
#include <soc/intel/common/lpss_i2c.h>
#include <device/i2c.h>
#include <soc/pm.h>
#include <soc/usb.h>
#define CLKREQ_DISABLED 0xf
#define APOLLOLAKE_I2C_DEV_MAX 8
@ -115,6 +116,10 @@ struct soc_intel_apollolake_config {
/* GPIO pin for PERST_0 */
uint16_t prt0_gpio;
/* USB2 eye diagram settings per port */
struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX];
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */

33
src/soc/intel/apollolake/include/soc/usb.h Normal file
View File

@ -0,0 +1,33 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corp.
* (Written by Kane Chen <Kane.Chen@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_APOLLOLAKE_USB_H_
#define _SOC_APOLLOLAKE_USB_H_
#define APOLLOLAKE_USB2_PORT_MAX 8
struct usb2_eye_per_port {
uint8_t Usb20PerPortTxPeHalf;
uint8_t Usb20PerPortPeTxiSet;
uint8_t Usb20PerPortTxiSet;
uint8_t Usb20HsSkewSel;
uint8_t Usb20IUsbTxEmphasisEn;
uint8_t Usb20PerPortRXISet;
uint8_t Usb20HsNpreDrvSel;
};
#endif /* _SOC_APOLLOLAKE_USB_H_ */