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chromeec: Add support for controlling USB port power 

This maps a bit field to the EC (EC_ACPI_MEM_USB_PORT_POWER) that can be
used to control the power state of up to 8 individual USB ports. Some
Chromeboxes have their GPIO pins for controlling USB port power wired to
the EC, so they cannot be accessed directly by coreboot.

Change-Id: I6a362c2b868b296031a4170c15e7c0dedbb870b8
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://review.coreboot.org/26471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Emil Lundmark 2018-05-22 19:31:37 +02:00 committed by Patrick Georgi
parent 5eec229d96
commit 9d5f9f2671
2 changed files with 28 additions and 0 deletions
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7
src/ec/google/chromeec/Kconfig
View File

@ -11,6 +11,13 @@ config EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
not defined, the memmap data is instead accessed on 900h-9ffh via
the LPC bus.
config EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER
depends on EC_GOOGLE_CHROMEEC
def_bool n
help
Expose methods for enabling and disabling port power on individual USB
ports through the EC.
config EC_GOOGLE_CHROMEEC_BOARDID
depends on EC_GOOGLE_CHROMEEC
def_bool n

21
src/ec/google/chromeec/acpi/ec.asl
View File

@ -91,6 +91,7 @@ Device (EC0)
Offset (0x0e),
Offset (0x12),
BTID, 8, // Battery index that host wants to read
USPP, 8, // USB Port Power
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
@ -512,6 +513,26 @@ Device (EC0)
Return (^TBMD)
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER)
/*
* Enable USB Port Power
* Arg0 = USB port ID
*/
Method (UPPS, 1, Serialized)
{
Or (USPP, ShiftLeft (1, Arg0), USPP)
}
/*
* Disable USB Port Power
* Arg0 = USB port ID
*/
Method (UPPC, 1, Serialized)
{
And (USPP, Not (ShiftLeft (1, Arg0)), USPP)
}
#endif
#include "ac.asl"
#include "battery.asl"
#include "cros_ec.asl"