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cpu/intel: Fix the spacing issues 

Fix the following errors and warnings detected by checkpatch.pl:

ERROR: spaces required around that '=' (ctx:VxV)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: need consistent spacing around '-' (ctx:WxV)
ERROR: spaces required around that '>' (ctx:VxV)
ERROR: need consistent spacing around '>>' (ctx:WxV)
ERROR: need consistent spacing around '<<' (ctx:VxW)
ERROR: spaces required around that '||' (ctx:VxV)
ERROR: "foo * bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
WARNING: space prohibited between function name and open parenthesis '('
WARNING: storage class should be at the beginning of the declaration

TEST=Build and run on Galileo Gen2

Change-Id: I6602fbc8602171ab6c2f3b6c204558ad2c811179
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18847
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2017-03-15 17:40:50 -07:00
parent 7b5f12b9b2
commit 9d62e7e75e
20 changed files with 51 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/intel/car/romstage.c
View File

@ -19,7 +19,7 @@
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
void * asmlinkage romstage_main(unsigned long bist)
asmlinkage void *romstage_main(unsigned long bist)
{
int i;
void *romstage_stack_after_car;
@ -47,7 +47,7 @@ void * asmlinkage romstage_main(unsigned long bist)
return romstage_stack_after_car;
}
void asmlinkage romstage_after_car(void)
asmlinkage void romstage_after_car(void)
{
/* Load the ramstage. */
run_ramstage();

4
src/cpu/intel/car/romstage_legacy.c
View File

@ -13,8 +13,8 @@
#include <cpu/intel/romstage.h>
void * asmlinkage romstage_main(unsigned long bist)
asmlinkage void *romstage_main(unsigned long bist)
{
mainboard_romstage_entry(bist);
return (void*)CONFIG_RAMTOP;
return (void *)CONFIG_RAMTOP;
}

4
src/cpu/intel/fsp_model_206ax/acpi.c
View File

@ -309,8 +309,8 @@ void generate_cpu_entries(device_t device)
numcpus, cores_per_package);
for (cpuID = 1; cpuID <= numcpus; cpuID++) {
for (coreID=1; coreID<=cores_per_package; coreID++) {
if (coreID>1) {
for (coreID = 1; coreID <= cores_per_package; coreID++) {
if (coreID > 1) {
pcontrol_blk = 0;
plen = 0;
}

4
src/cpu/intel/fsp_model_406dx/acpi.c
View File

@ -270,8 +270,8 @@ void generate_cpu_entries(device_t device)
numcpus, cores_per_package);
for (cpuID = 1; cpuID <= numcpus; cpuID++) {
for (coreID=1; coreID<=cores_per_package; coreID++) {
if (coreID>1) {
for (coreID = 1; coreID <= cores_per_package; coreID++) {
if (coreID > 1) {
pcontrol_blk = 0;
plen = 0;
}

4
src/cpu/intel/fsp_model_406dx/bootblock.c
View File

@ -36,8 +36,8 @@ static void check_for_warm_reset(void)
* Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set.
* If either is true, then this is a warm reset so execute a Hard Reset
*/
if ( (inb(0xcf9) == 0x04) ||
(pci_io_read_config32(SOC_LPC_DEV, RCBA) & RCBA_ENABLE) ) {
if ((inb(0xcf9) == 0x04) ||
(pci_io_read_config32(SOC_LPC_DEV, RCBA) & RCBA_ENABLE)) {
outb(0x00, 0xcf9);
outb(0x06, 0xcf9);
}

4
src/cpu/intel/haswell/acpi.c
View File

@ -314,8 +314,8 @@ void generate_cpu_entries(device_t device)
numcpus, cores_per_package);
for (cpuID = 1; cpuID <= numcpus; cpuID++) {
for (coreID=1; coreID<=cores_per_package; coreID++) {
if (coreID>1) {
for (coreID = 1; coreID <= cores_per_package; coreID++) {
if (coreID > 1) {
pcontrol_blk = 0;
plen = 0;
}

4
src/cpu/intel/haswell/haswell.h
View File

@ -180,10 +180,10 @@ void romstage_common(const struct romstage_params *params);
* +32: MTRR mask 1 63:32
* ...
*/
void * asmlinkage romstage_main(unsigned long bist);
asmlinkage void *romstage_main(unsigned long bist);
/* romstage_after_car() is the C function called after cache-as-ram has
* been torn down. It is responsible for loading the ramstage. */
void asmlinkage romstage_after_car(void);
asmlinkage void romstage_after_car(void);
#endif
#ifdef __SMM__

4
src/cpu/intel/haswell/haswell_init.c
View File

@ -87,12 +87,12 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = {
[C_STATE_C1] = {
.latency = 0,
.power = 1000,
.resource = MWAIT_RES(0,0),
.resource = MWAIT_RES(0, 0),
},
[C_STATE_C1E] = {
.latency = 0,
.power = 1000,
.resource = MWAIT_RES(0,1),
.resource = MWAIT_RES(0, 1),
},
[C_STATE_C3] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(0),

4
src/cpu/intel/haswell/romstage.c
View File

@ -140,7 +140,7 @@ static void *setup_romstage_stack_after_car(void)
return slot;
}
void * asmlinkage romstage_main(unsigned long bist)
asmlinkage void *romstage_main(unsigned long bist)
{
int i;
void *romstage_stack_after_car;
@ -253,7 +253,7 @@ void romstage_common(const struct romstage_params *params)
}
}
void asmlinkage romstage_after_car(void)
asmlinkage void romstage_after_car(void)
{
/* Load the ramstage. */
run_ramstage();

2
src/cpu/intel/hyperthreading/intel_sibling.c
View File

@ -77,7 +77,7 @@ void intel_sibling_init(struct device *cpu)
siblings);
/* See if I am a sibling cpu */
if (cpu->path.apic.apic_id & (siblings -1)) {
if (cpu->path.apic.apic_id & (siblings - 1)) {
if (disable_siblings) {
cpu->enabled = 0;
}

6
src/cpu/intel/microcode/microcode.c
View File

@ -145,12 +145,12 @@ const void *intel_microcode_find(void)
eax = cpuid_eax(1);
msr = rdmsr(0x8B);
rev = msr.hi;
x86_model = (eax >>4) & 0x0f;
x86_family = (eax >>8) & 0x0f;
x86_model = (eax >> 4) & 0x0f;
x86_family = (eax >> 8) & 0x0f;
sig = eax;
pf = 0;
if ((x86_model >= 5)||(x86_family>6)) {
if ((x86_model >= 5) || (x86_family > 6)) {
msr = rdmsr(0x17);
pf = 1 << ((msr.hi >> 18) & 7);
}

2
src/cpu/intel/model_1067x/model_1067x_init.c
View File

@ -33,7 +33,7 @@
static void init_timer(void)
{
/* Set the APIC timer to no interrupts and periodic mode */
lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
lapic_write(LAPIC_LVTT, (1 << 17) | (1 << 16) | (0 << 12) | (0 << 0));
/* Set the divider to 1, no divider */
lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);

4
src/cpu/intel/model_2065x/acpi.c
View File

@ -306,8 +306,8 @@ void generate_cpu_entries(device_t device)
numcpus, cores_per_package);
for (cpuID = 1; cpuID <= numcpus; cpuID++) {
for (coreID=1; coreID<=cores_per_package; coreID++) {
if (coreID>1) {
for (coreID = 1; coreID <= cores_per_package; coreID++) {
if (coreID > 1) {
pcontrol_blk = 0;
plen = 0;
}

5
src/cpu/intel/model_2065x/model_2065x_init.c
View File

@ -42,7 +42,7 @@
*/
static acpi_cstate_t cstate_map[] = {
{ /* 0: C0 */
},{ /* 1: C1 */
}, { /* 1: C1 */
.latency = 1,
.power = 1000,
.resource = {
@ -321,7 +321,8 @@ static void model_2065x_init(struct device *cpu)
/* Print processor name */
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid (), boot_cpu ());
printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid(),
boot_cpu());
/* Setup MTRRs based on physical address size */
x86_setup_mtrrs_with_detect();

4
src/cpu/intel/model_206ax/acpi.c
View File

@ -309,8 +309,8 @@ void generate_cpu_entries(device_t device)
numcpus, cores_per_package);
for (cpuID = 1; cpuID <= numcpus; cpuID++) {
for (coreID=1; coreID<=cores_per_package; coreID++) {
if (coreID>1) {
for (coreID = 1; coreID <= cores_per_package; coreID++) {
if (coreID > 1) {
pcontrol_blk = 0;
plen = 0;
}

2
src/cpu/intel/model_206ax/model_206ax_init.c
View File

@ -42,7 +42,7 @@
*/
static acpi_cstate_t cstate_map[] = {
{ /* 0: C0 */
},{ /* 1: C1 */
}, { /* 1: C1 */
.latency = 1,
.power = 1000,
.resource = {

4
src/cpu/intel/model_6ex/model_6ex_init.c
View File

@ -85,10 +85,10 @@ static void configure_misc(void)
// set maximum CPU speed
msr = rdmsr(IA32_PERF_STS);
int busratio_max=(msr.hi >> (40-32)) & 0x1f;
int busratio_max = (msr.hi >> (40-32)) & 0x1f;
msr = rdmsr(IA32_PLATFORM_ID);
int vid_max=msr.lo & 0x3f;
int vid_max = msr.lo & 0x3f;
msr.lo &= ~0xffff;
msr.lo |= busratio_max << 8;

4
src/cpu/intel/model_6fx/model_6fx_init.c
View File

@ -93,10 +93,10 @@ static void configure_misc(void)
// set maximum CPU speed
msr = rdmsr(IA32_PERF_STS);
int busratio_max=(msr.hi >> (40-32)) & 0x1f;
int busratio_max = (msr.hi >> (40-32)) & 0x1f;
msr = rdmsr(IA32_PLATFORM_ID);
int vid_max=msr.lo & 0x3f;
int vid_max = msr.lo & 0x3f;
msr.lo &= ~0xffff;
msr.lo |= busratio_max << 8;

28
src/cpu/intel/slot_1/l2_cache.c
View File

@ -133,7 +133,7 @@ int calculate_l2_latency(void)
*/
msr = rdmsr(IA32_PLATFORM_ID);
printk(BIOS_DEBUG,"rdmsr(IA32_PLATFORM_ID) = %x:%x\n", msr.hi, msr.lo);
printk(BIOS_DEBUG, "rdmsr(IA32_PLATFORM_ID) = %x:%x\n", msr.hi, msr.lo);
l = (msr.hi >> 20) & 0x1e;
@ -160,7 +160,7 @@ int calculate_l2_latency(void)
else
return -1;
printk(BIOS_DEBUG,"L2 latency type = %x\n", t);
printk(BIOS_DEBUG, "L2 latency type = %x\n", t);
/* Get CPUID family/model */
signature = cpuid_eax(1) & 0xfff0;
@ -193,7 +193,7 @@ int calculate_l2_latency(void)
l = le->value;
}
printk(BIOS_DEBUG,"L2 Cache latency is %d\n", l / 2);
printk(BIOS_DEBUG, "L2 Cache latency is %d\n", l / 2);
/* Writes the calculated latency in BBL_CR_CTL3[4:1]. */
msr = rdmsr(BBL_CR_CTL3);
@ -385,7 +385,7 @@ int calculate_l2_cache_size(void)
wrmsr(BBL_CR_CTL3, msr);
printk(BIOS_DEBUG,"Maximum cache mask is %x\n", cache_setting);
printk(BIOS_DEBUG, "Maximum cache mask is %x\n", cache_setting);
/* For now, BBL_CR_CTL3 has the highest cache "size" that register
* will accept. Now we'll ping the cache and see where it wraps.
@ -432,7 +432,7 @@ int calculate_l2_cache_size(void)
msr.lo |= size;
wrmsr(BBL_CR_CTL3, msr);
printk(BIOS_DEBUG,"L2 Cache Mask is %x\n", size);
printk(BIOS_DEBUG, "L2 Cache Mask is %x\n", size);
/* Shift to [6:2] */
size >>= 11;
@ -442,7 +442,7 @@ int calculate_l2_cache_size(void)
if (v < 0)
return -1;
printk(BIOS_DEBUG,"L2(2): %x ", v);
printk(BIOS_DEBUG, "L2(2): %x ", v);
v &= 0x3;
@ -452,7 +452,7 @@ int calculate_l2_cache_size(void)
/* Or in this size */
v |= size;
printk(BIOS_DEBUG,"-> %x\n", v);
printk(BIOS_DEBUG, "-> %x\n", v);
if (write_l2(2, v) != 0)
return -1;
@ -463,7 +463,7 @@ int calculate_l2_cache_size(void)
v = read_l2(2);
printk(BIOS_DEBUG,"L2(2) = %x\n", v);
printk(BIOS_DEBUG, "L2(2) = %x\n", v);
if (v < 0)
return -1;
@ -476,7 +476,7 @@ int calculate_l2_cache_size(void)
v &= 0xf;
printk(BIOS_DEBUG,"Calculated a = %x\n", v);
printk(BIOS_DEBUG, "Calculated a = %x\n", v);
if (v == 0)
return -1;
@ -513,7 +513,7 @@ int calculate_l2_physical_address_range(void)
else
r3 &= 0x7;
printk(BIOS_DEBUG,"L2 Physical Address Range is %dM\n", (1 << r3) * 512);
printk(BIOS_DEBUG, "L2 Physical Address Range is %dM\n", (1 << r3) * 512);
/* Shift into [22:20] to be saved into BBL_CR_CTL3. */
r3 = r3 << 20;
@ -551,7 +551,7 @@ int set_l2_ecc(void)
eax = msr.lo;
if (eax == data1) {
printk(BIOS_DEBUG,"L2 ECC Checking is enabled\n");
printk(BIOS_DEBUG, "L2 ECC Checking is enabled\n");
/* Set ECC Check Enable in BBL_CR_CTL3 */
msr = rdmsr(BBL_CR_CTL3);
@ -591,7 +591,7 @@ int p6_configure_l2_cache(void)
/* If bit 23 (L2 Hardware disable) is set then done */
/* These would be Covington core Celerons with no L2 cache */
if (bblctl3.lo & BBLCR3_L2_NOT_PRESENT) {
printk(BIOS_INFO,"hardware disabled\n");
printk(BIOS_INFO, "hardware disabled\n");
return 0;
}
@ -666,7 +666,7 @@ int p6_configure_l2_cache(void)
v = (calc_eax >> 26) & 0x3;
printk(BIOS_DEBUG,"write_l2(4, %x)\n", v);
printk(BIOS_DEBUG, "write_l2(4, %x)\n", v);
a = read_l2(4);
if (a >= 0)
@ -772,7 +772,7 @@ int p6_configure_l2_cache(void)
/* Write 0 to L2 control register 5 */
if (write_l2(5, 0) != 0) {
printk(BIOS_ERR,"write_l2(5, 0) failed\n");
printk(BIOS_ERR, "write_l2(5, 0) failed\n");
goto done;
}

4
src/cpu/intel/speedstep/acpi.c
View File

@ -139,8 +139,8 @@ void generate_cpu_entries(device_t device)
coordination = SW_ANY;
for (cpuID = 0; cpuID < numcpus; ++cpuID) {
for (coreID=1; coreID<=cores_per_package; coreID++) {
if (coreID>1) {
for (coreID = 1; coreID <= cores_per_package; coreID++) {
if (coreID > 1) {
pcontrol_blk = 0;
plen = 0;
}