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mb/google/brya: Update mainboard properties for BB retimer upgrade 

This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.

Reference CB:54292

BUG=b:186521258
TEST=Updated BB retimer FW from 3.4 to 3.5 without any device
connected.

Change-Id: I24a02fd446cb66bda9e66e59802b4deea6894273
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Maulik V Vaghela 2021-06-09 14:03:08 +05:30 committed by Werner Zeh
parent b34950e68a
commit 9e23d017f5
2 changed files with 17 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/brya/Kconfig
View File

@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_DPTF
select DRIVERS_INTEL_PMC select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_INTEL_SOUNDWIRE
select DRIVERS_INTEL_USB4_RETIMER
select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_SOUNDWIRE_ALC5682
select DRIVERS_SOUNDWIRE_MAX98373 select DRIVERS_SOUNDWIRE_MAX98373
select DRIVERS_SPI_ACPI select DRIVERS_SPI_ACPI

16
src/mainboard/google/brya/variants/brya0/overridetree.cb
View File

@ -134,6 +134,22 @@ chip soc/intel/alderlake
device ref pcie_rp6 on device ref pcie_rp6 on
probe DB_LTE LTE_PCIE probe DB_LTE LTE_PCIE
end end
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp" = "{
[0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4),
.group = ACPI_PLD_GROUP(1, 1),}}"
device generic 0 on end
end
end
device ref tcss_dma1 on
chip drivers/intel/usb4/retimer
register "dfp" = "{
[0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4),
.group = ACPI_PLD_GROUP(3, 1)}}"
device generic 0 on end
end
end
device ref pcie_rp8 on device ref pcie_rp8 on
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"