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soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS 

a) Add LTR disqualification in D3 to ensure PMC ignores LTR
from UFS IP as it is infinite.
b) Remove LTR disqualification in _PS0 to ensure PMC stops
ignoring LTR from UFS IP during D3 exit.
c) Add Kconfig (SOC_INTEL_UFS_LTR_DISQUALIFY) check to apply
this LTR WA.

BUG=b:252975357
TEST=build and boot nirwen and see no issues in PLT runs

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Meera Ravindranath 2022-10-10 10:48:18 +05:30 committed by Felix Held
parent a00db94270
commit 9e4488ab06
4 changed files with 34 additions and 1 deletions
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1
src/soc/intel/alderlake/Kconfig
View File

@ -428,6 +428,7 @@ config ACPI_ADL_IPU_ES_SUPPORT
config ALDERLAKE_ENABLE_SOC_WORKAROUND config ALDERLAKE_ENABLE_SOC_WORKAROUND
bool bool
default y default y
select SOC_INTEL_UFS_LTR_DISQUALIFY
select SOC_INTEL_UFS_OCP_TIMER_DISABLE select SOC_INTEL_UFS_OCP_TIMER_DISABLE
help help
Selects the workarounds applicable for Alder Lake SoC. Selects the workarounds applicable for Alder Lake SoC.

3
src/soc/intel/alderlake/include/soc/ufs.h
View File

@ -22,6 +22,7 @@
#define R_SCS_PCR_5820 0x5820 #define R_SCS_PCR_5820 0x5820
#define R_SCS_PCR_5C20 0x5C20 #define R_SCS_PCR_5C20 0x5C20
#define R_SCS_PCR_1078 0x1078 #define R_SCS_PCR_1078 0x1078
#define R_PMC_PWRM_LTR_IGN 0x1B0C
#define R_PMC_PWRM_LTR_IGN 0x1b0c
#define PCH_PWRM_BASE_SIZE 0x1e30
#endif #endif

5
src/soc/intel/common/block/acpi/Kconfig
View File

@ -56,4 +56,9 @@ config SOC_INTEL_UFS_OCP_TIMER_DISABLE
work around the Silicon Issue due to which LTR mechanism work around the Silicon Issue due to which LTR mechanism
doesn't work. doesn't work.
config SOC_INTEL_UFS_LTR_DISQUALIFY
bool
help
LTR needs to be disqualified for UFS in D3 to ensure PMC
ignores LTR from UFS IP which is infinite.
endif endif

26
src/soc/intel/common/block/acpi/acpi/ufs.asl
View File

@ -1,7 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/iomap.h>
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
#include <soc/ufs.h> #include <soc/ufs.h>
#define TRUE 1
#define FALSE 0
Scope (\_SB.PCI0) Scope (\_SB.PCI0)
{ {
Device (UFS) Device (UFS)
@ -59,6 +63,18 @@ Scope (\_SB.PCI0)
PGEN, 1 PGEN, 1
} }
OperationRegion(PWMR, SystemMemory, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE)
Field(PWMR, DWordAcc, NoLock, Preserve)
{
Offset(R_PMC_PWRM_LTR_IGN),
, 18,
LTRU, 1, /* Bit 18 - Ignore LTR from UFS X2 */
}
Method (ULTR, 1, Serialized) {
LTRU = Arg0
}
Method (_PS0, 0, Serialized) Method (_PS0, 0, Serialized)
{ {
/* Disable PG */ /* Disable PG */
@ -67,6 +83,11 @@ Scope (\_SB.PCI0)
/* Set BIT[1:0] = 00b - Power State D0 */ /* Set BIT[1:0] = 00b - Power State D0 */
PSTA &= 0xFFFFFFFC PSTA &= 0xFFFFFFFC
#if CONFIG(SOC_INTEL_UFS_LTR_DISQUALIFY)
/* Remove Disqualification of LTR from UFS IP */
ULTR (FALSE)
#endif
#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE) #if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE)
/* Disable OCP Timer in SCS UFS IOSF Bridge */ /* Disable OCP Timer in SCS UFS IOSF Bridge */
OCPD () OCPD ()
@ -75,6 +96,11 @@ Scope (\_SB.PCI0)
Method (_PS3, 0, Serialized) Method (_PS3, 0, Serialized)
{ {
#if CONFIG(SOC_INTEL_UFS_LTR_DISQUALIFY)
/* Disqualify LTR from UFS IP */
ULTR (TRUE)
#endif
/* Enable PG */ /* Enable PG */
PGEN = 1 PGEN = 1
} }