cpu/x86/lapic: Move LAPIC configuration to MP init

Implementation for setup_lapic() did two things -- call
enable_lapic() and virtual_wire_mode_init().

In PARALLEL_MP case enable_lapic() was redundant as it
was already executed prior to initialize_cpu() call.
For the !PARALLEL_MP case enable_lapic() is added to
AP CPUs.

Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/cpu/amd/agesa/family14/model_14_init.c

@@ -7,7 +7,6 @@
 #include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <cpu/x86/pae.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <acpi/acpi.h>
@@ -57,9 +56,6 @@ static void model_14_init(struct device *dev)
 	/* zero the machine check error status registers */
 	mca_clear_status();
 
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
 #if CONFIG(LOGICAL_CPUS)
 	siblings = cpuid_ecx(0x80000008) & 0xff;
 

src/cpu/amd/agesa/family15tn/model_15_init.c

@@ -8,7 +8,6 @@
 #include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <cpu/x86/pae.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <acpi/acpi.h>
@@ -59,9 +58,6 @@ static void model_15_init(struct device *dev)
 	/* zero the machine check error status registers */
 	mca_clear_status();
 
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
 #if CONFIG(LOGICAL_CPUS)
 	siblings = cpuid_ecx(0x80000008) & 0xff;
 

src/cpu/amd/agesa/family16kb/model_16_init.c

@@ -7,7 +7,6 @@
 #include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <cpu/x86/pae.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <acpi/acpi.h>
@@ -57,9 +56,6 @@ static void model_16_init(struct device *dev)
 	/* zero the machine check error status registers */
 	mca_clear_status();
 
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
 #if CONFIG(LOGICAL_CPUS)
 	siblings = cpuid_ecx(0x80000008) & 0xff;
 

src/cpu/amd/pi/00730F01/model_16_init.c

@@ -11,7 +11,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <cpu/x86/pae.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <smp/node.h>
@@ -26,9 +25,6 @@ static void model_16_init(struct device *dev)
 	/* zero the machine check error status registers */
 	mca_clear_status();
 
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
 	if (CONFIG(LOGICAL_CPUS)) {
 		siblings = cpuid_ecx(0x80000008) & 0xff;
 

src/cpu/intel/common/common_init.c

@@ -4,7 +4,6 @@
 #include <arch/cpu.h>
 #include <console/console.h>
 #include <cpu/intel/msr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 #include "common.h"
 

src/cpu/intel/haswell/haswell_init.c

@@ -7,7 +7,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mp.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/speedstep.h>
@@ -541,9 +540,7 @@ static void cpu_core_init(struct device *cpu)
 	/* Clear out pending MCEs */
 	configure_mca();
 
-	/* Enable the local CPU APICs */
 	enable_lapic_tpr();
-	setup_lapic();
 
 	/* Set virtualization based on Kconfig option */
 	set_vmx_and_lock();

src/cpu/intel/model_1067x/model_1067x_init.c

@@ -4,7 +4,6 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
@@ -256,9 +255,6 @@ static void model_1067x_init(struct device *cpu)
 	fill_processor_name(processor_name);
 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
 	/* Configure C States */
 	configure_c_states(quad);
 

src/cpu/intel/model_106cx/model_106cx_init.c

@@ -4,7 +4,6 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
@@ -67,9 +66,6 @@ static void model_106cx_init(struct device *cpu)
 	fill_processor_name(processor_name);
 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
 	/* Configure C States */
 	configure_c_states();
 

src/cpu/intel/model_2065x/model_2065x_init.c

@@ -91,9 +91,7 @@ static void model_2065x_init(struct device *cpu)
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
-	/* Enable the local CPU APICs */
 	enable_lapic_tpr();
-	setup_lapic();
 
 	/* Set virtualization based on Kconfig option */
 	set_vmx_and_lock();

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -7,7 +7,6 @@
 #include <cpu/cpu.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/speedstep.h>
@@ -338,9 +337,7 @@ static void model_206ax_init(struct device *cpu)
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
-	/* Enable the local CPU APICs */
 	enable_lapic_tpr();
-	setup_lapic();
 
 	/* Set virtualization based on Kconfig option */
 	set_vmx_and_lock();

src/cpu/intel/model_65x/model_65x_init.c

@@ -3,7 +3,6 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 #include <cpu/intel/l2_cache.h>
@@ -19,9 +18,6 @@ static void model_65x_init(struct device *dev)
 	enable_cache();
 	x86_setup_mtrrs();
 	x86_mtrr_check();
-
-	/* Enable the local CPU APICs */
-	setup_lapic();
 };
 
 static struct device_operations cpu_dev_ops = {

src/cpu/intel/model_67x/model_67x_init.c

@@ -3,7 +3,6 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 #include <cpu/intel/l2_cache.h>
@@ -22,9 +21,6 @@ static void model_67x_init(struct device *cpu)
 	/* Setup MTRRs */
 	x86_setup_mtrrs();
 	x86_mtrr_check();
-
-	/* Enable the local CPU APICs */
-	setup_lapic();
 }
 
 static struct device_operations cpu_dev_ops = {

src/cpu/intel/model_68x/model_68x_init.c

@@ -4,7 +4,6 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
@@ -26,9 +25,6 @@ static void model_68x_init(struct device *cpu)
 	/* Setup MTRRs */
 	x86_setup_mtrrs();
 	x86_mtrr_check();
-
-	/* Enable the local CPU APICs */
-	setup_lapic();
 }
 
 static struct device_operations cpu_dev_ops = {

src/cpu/intel/model_6bx/model_6bx_init.c

@@ -4,7 +4,6 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
@@ -26,9 +25,6 @@ static void model_6bx_init(struct device *cpu)
 	/* Setup MTRRs */
 	x86_setup_mtrrs();
 	x86_mtrr_check();
-
-	/* Enable the local CPU APICs */
-	setup_lapic();
 }
 
 static struct device_operations cpu_dev_ops = {

src/cpu/intel/model_6ex/model_6ex_init.c

@@ -4,7 +4,6 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
@@ -106,9 +105,6 @@ static void model_6ex_init(struct device *cpu)
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
 	/* Configure C States */
 	configure_c_states();
 

src/cpu/intel/model_6fx/model_6fx_init.c

@@ -4,7 +4,6 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
@@ -120,9 +119,6 @@ static void model_6fx_init(struct device *cpu)
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
 	/* Configure C States */
 	configure_c_states();
 

src/cpu/intel/model_6xx/model_6xx_init.c

@@ -3,7 +3,6 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 
@@ -16,9 +15,6 @@ static void model_6xx_init(struct device *dev)
 
 	/* Update the microcode */
 	intel_update_microcode_from_cbfs();
-
-	/* Enable the local CPU APICs */
-	setup_lapic();
 };
 
 static struct device_operations cpu_dev_ops = {

src/cpu/intel/model_f2x/model_f2x_init.c

@@ -3,7 +3,6 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/hyperthreading.h>
 #include <cpu/intel/common/common.h>
@@ -23,9 +22,6 @@ static void model_f2x_init(struct device *cpu)
 		intel_update_microcode_from_cbfs();
 	}
 
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
 	/* Start up my CPU siblings */
 	intel_sibling_init(cpu);
 };

src/cpu/intel/model_f3x/model_f3x_init.c

@@ -3,7 +3,6 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/hyperthreading.h>
 #include <cpu/intel/common/common.h>
@@ -23,9 +22,6 @@ static void model_f3x_init(struct device *cpu)
 		intel_update_microcode_from_cbfs();
 	}
 
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
 	/* Start up my CPU siblings */
 	if (!CONFIG(PARALLEL_MP))
 		intel_sibling_init(cpu);

src/cpu/intel/model_f4x/model_f4x_init.c

@@ -2,16 +2,12 @@
 
 #include <device/device.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/cache.h>
 
 static void model_f4x_init(struct device *cpu)
 {
 	/* Turn on caching if we haven't already */
 	enable_cache();
-
-	/* Enable the local CPU APICs */
-	setup_lapic();
 };
 
 static struct device_operations cpu_dev_ops = {

src/cpu/qemu-x86/qemu.c

@@ -2,11 +2,9 @@
 
 #include <cpu/cpu.h>
 #include <device/device.h>
-#include <cpu/x86/lapic.h>
 
 static void qemu_cpu_init(struct device *dev)
 {
-	setup_lapic();
 }
 
 static struct device_operations cpu_dev_ops = {

src/cpu/x86/lapic/lapic.c

@@ -65,13 +65,7 @@ uintptr_t cpu_get_lapic_addr(void)
 	return LAPIC_DEFAULT_BASE;
 }
 
-/* See if I need to initialize the local APIC */
-static int need_lapic_init(void)
-{
-	return CONFIG(SMP) || CONFIG(IOAPIC);
-}
-
-static void lapic_virtual_wire_mode_init(void)
+void setup_lapic_interrupts(void)
 {
 	/*
 	 * Set Task Priority to 'accept all'.
@@ -94,17 +88,3 @@ static void lapic_virtual_wire_mode_init(void)
 
 	lapic_update32(LAPIC_LVT1, ~mask, LAPIC_DELIVERY_MODE_NMI);
 }
-
-void setup_lapic(void)
-{
-	/* Enable the local APIC */
-	if (need_lapic_init())
-		enable_lapic();
-	else if (!CONFIG(UDELAY_LAPIC))
-		disable_lapic();
-
-	/* This programming is for PIC mode i8259 interrupts to be delivered to CPU
-	   while LAPIC is enabled. */
-	if (need_lapic_init())
-		lapic_virtual_wire_mode_init();
-}

src/cpu/x86/lapic/lapic_cpu_init.c

@@ -298,6 +298,11 @@ asmlinkage void secondary_cpu_init(unsigned int index)
 	cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT);
 	write_cr4(cr4_val);
 #endif
+
+	/* Ensure the local APIC is enabled */
+	enable_lapic();
+	setup_lapic_interrupts();
+
 	cpu_initialize(index);
 
 	spin_unlock(&start_cpu_lock);
@@ -376,8 +381,10 @@ void initialize_cpus(struct bus *cpu_bus)
 	info = cpu_info();
 
 	/* Ensure the local APIC is enabled */
-	if (is_smp_boot())
+	if (is_smp_boot()) {
 		enable_lapic();
+		setup_lapic_interrupts();
+	}
 
 	/* Get the device path of the boot CPU */
 	cpu_path.type = DEVICE_PATH_APIC;

src/cpu/x86/mp_init.c

@@ -185,6 +185,7 @@ static void asmlinkage ap_init(void)
 
 	/* Ensure the local APIC is enabled */
 	enable_lapic();
+	setup_lapic_interrupts();
 
 	info->cpu = cpus_dev[info->index];
 
@@ -543,6 +544,7 @@ static void init_bsp(struct bus *cpu_bus)
 
 	/* Ensure the local APIC is enabled */
 	enable_lapic();
+	setup_lapic_interrupts();
 
 	/* Set the device path of the boot CPU. */
 	cpu_path.type = DEVICE_PATH_APIC;

src/include/cpu/x86/lapic.h

@@ -177,6 +177,6 @@ void stop_this_cpu(void);
 
 void enable_lapic(void);
 void disable_lapic(void);
-void setup_lapic(void);
+void setup_lapic_interrupts(void);
 
 #endif /* CPU_X86_LAPIC_H */

src/soc/amd/cezanne/cpu.c

@@ -8,7 +8,6 @@
 #include <console/console.h>
 #include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
@@ -62,7 +61,6 @@ void mp_init_cpus(struct bus *cpu_bus)
 static void zen_2_3_init(struct device *dev)
 {
 	check_mca();
-	setup_lapic();
 	set_cstate_io_addr();
 
 	amd_update_microcode_from_cbfs();

src/soc/amd/picasso/cpu.c

@@ -10,7 +10,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/smm.h>
-#include <cpu/x86/lapic.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
@@ -66,7 +65,6 @@ void mp_init_cpus(struct bus *cpu_bus)
 static void model_17_init(struct device *dev)
 {
 	check_mca();
-	setup_lapic();
 	set_cstate_io_addr();
 
 	amd_update_microcode_from_cbfs();

src/soc/amd/sabrina/cpu.c

@@ -10,7 +10,6 @@
 #include <console/console.h>
 #include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
@@ -64,7 +63,6 @@ void mp_init_cpus(struct bus *cpu_bus)
 static void zen_2_3_init(struct device *dev)
 {
 	check_mca();
-	setup_lapic();
 	set_cstate_io_addr();
 
 	amd_update_microcode_from_cbfs();

src/soc/amd/stoneyridge/cpu.c

@@ -9,7 +9,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/smm.h>
-#include <cpu/x86/lapic.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
@@ -65,7 +64,6 @@ void mp_init_cpus(struct bus *cpu_bus)
 static void model_15_init(struct device *dev)
 {
 	check_mca();
-	setup_lapic();
 
 	/*
 	 * Per AMD, sync an undocumented MSR with the PSP base address.

src/soc/intel/alderlake/cpu.c

@@ -9,7 +9,6 @@
 #include <console/console.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/smm_reloc.h>
@@ -110,9 +109,7 @@ void soc_core_init(struct device *cpu)
 	 * every bank. */
 	mca_configure();
 
-	/* Enable the local CPU apics */
 	enable_lapic_tpr();
-	setup_lapic();
 
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();

src/soc/intel/apollolake/cpu.c

@@ -5,7 +5,6 @@
 #include <console/console.h>
 #include "chip.h"
 #include <cpu/cpu.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/turbo.h>
@@ -154,8 +153,6 @@ static void pre_mp_init(void)
 	x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();
 
-	/* Enable the local CPU apics */
-	setup_lapic();
 }
 
 #if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)

src/soc/intel/baytrail/cpu.c

@@ -36,9 +36,6 @@ static void soc_core_init(struct device *cpu)
 {
 	printk(BIOS_DEBUG, "Init BayTrail core.\n");
 
-	/* Enable the local CPU apics */
-	setup_lapic();
-
 	/*
 	 * The turbo disable bit is actually scoped at building block level -- not package.
 	 * For non-BSP cores that are within a building block, enable turbo. The cores within

src/soc/intel/braswell/cpu.c

@@ -36,9 +36,6 @@ static void soc_core_init(struct device *cpu)
 {
 	printk(BIOS_DEBUG, "Init Braswell core.\n");
 
-	/* Enable the local cpu apics */
-	setup_lapic();
-
 	/*
 	 * The turbo disable bit is actually scoped at building block level -- not package.
 	 * For non-BSP cores that are within a building block, enable turbo. The cores within

src/soc/intel/cannonlake/cpu.c

@@ -2,7 +2,6 @@
 
 #include <console/console.h>
 #include <device/pci.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/smm_reloc.h>
@@ -118,9 +117,7 @@ void soc_core_init(struct device *cpu)
 	 * every bank. */
 	mca_configure();
 
-	/* Enable the local CPU apics */
 	enable_lapic_tpr();
-	setup_lapic();
 
 	/* Configure c-state interrupt response time */
 	configure_c_states(cfg);

src/soc/intel/denverton_ns/cpu.c

@@ -100,9 +100,6 @@ static void denverton_core_init(struct device *cpu)
 	/* Enable Turbo */
 	enable_turbo();
 
-	/* Enable the local CPU apics */
-	setup_lapic();
-
 	/* Enable speed step. Always ON.*/
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= SPEED_STEP_ENABLE_BIT;

src/soc/intel/elkhartlake/cpu.c

@@ -3,7 +3,6 @@
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/intel/common/common.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <device/pci.h>
@@ -70,9 +69,7 @@ void soc_core_init(struct device *cpu)
 	 * every bank. */
 	mca_configure();
 
-	/* Enable the local CPU apics */
 	enable_lapic_tpr();
-	setup_lapic();
 
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();

src/soc/intel/icelake/cpu.c

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/pci.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/smm_reloc.h>
@@ -103,9 +102,7 @@ void soc_core_init(struct device *cpu)
 	 * every bank. */
 	mca_configure();
 
-	/* Enable the local CPU apics */
 	enable_lapic_tpr();
-	setup_lapic();
 
 	/* Configure c-state interrupt response time */
 	configure_c_states();

src/soc/intel/jasperlake/cpu.c

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/pci.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/smm_reloc.h>
@@ -70,9 +69,7 @@ void soc_core_init(struct device *cpu)
 	 * every bank. */
 	mca_configure();
 
-	/* Enable the local CPU apics */
 	enable_lapic_tpr();
-	setup_lapic();
 
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();

src/soc/intel/skylake/cpu.c

@@ -5,7 +5,6 @@
 #include <device/pci.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/intel/microcode.h>
@@ -118,9 +117,7 @@ void soc_core_init(struct device *cpu)
 	 * every bank. */
 	mca_configure();
 
-	/* Enable the local CPU apics */
 	enable_lapic_tpr();
-	setup_lapic();
 
 	/* Configure c-state interrupt response time */
 	configure_c_states();

src/soc/intel/tigerlake/cpu.c

@@ -7,7 +7,6 @@
  */
 
 #include <device/pci.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/smm_reloc.h>
@@ -76,9 +75,7 @@ void soc_core_init(struct device *cpu)
 	 * every bank. */
 	mca_configure();
 
-	/* Enable the local CPU apics */
 	enable_lapic_tpr();
-	setup_lapic();
 
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();

src/soc/intel/xeon_sp/cpx/chip.c

@@ -3,7 +3,6 @@
 #include <arch/ioapic.h>
 #include <console/console.h>
 #include <console/debug.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -181,7 +180,6 @@ static void chip_init(void *data)
 	override_hpet_ioapic_bdf();
 	pch_enable_ioapic();
 	pch_lock_dmictl();
-	setup_lapic();
 	p2sb_unhide();
 }
 

src/soc/intel/xeon_sp/cpx/cpu.c

@@ -11,7 +11,6 @@
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/turbo.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/mtrr.h>
 #include <intelblocks/cpulib.h>
@@ -78,7 +77,6 @@ static void each_cpu_init(struct device *cpu)
 
 	printk(BIOS_SPEW, "%s dev: %s, cpu: %d, apic_id: 0x%x\n",
 		__func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id);
-	setup_lapic();
 
 	/*
 	 * Set HWP base feature, EPP reg enumeration, lock thermal and msr