soc/intel/tigerlake: Run pmc_set_acpi_mode() during .init in pmc_ops
pmc_set_acpi_mode() should run after Chrome EC dealt with all host event bits, like SMI mask (otherwise the FAFT firmware_FWScreenCloseLid test will fail). BUG=b:153249055 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Change the GBB flag to 0x140 then check SMI mask during depthcharge phase, make sure it's 0x0000000000000001. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: Icfff5cc5550f23938343e4d26ef76093bb9cf7c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -77,8 +77,6 @@ static void pmc_init(struct device *dev)
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pmc_set_power_failure_state(true);
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pmc_gpe_init();
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pmc_set_acpi_mode();
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config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
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config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
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config_deep_sx(config->deep_sx_config);
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@ -142,9 +140,24 @@ const struct device *soc_get_pmc_mux_device(int port_number)
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return child;
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}
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static void soc_acpi_mode_init(struct device *dev)
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{
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/*
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* pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
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* to ensure the ordering does not break the assumptions that other
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* drivers make about ACPI mode (e.g. Chrome EC). Since it disables
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* ACPI mode, other drivers may take different actions based on this
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* (e.g. Chrome EC will flush any pending hostevent bits). Because
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* TGL has its PMC device available for device_operations, it can be
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* done from the "ops->init" callback.
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*/
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pmc_set_acpi_mode();
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}
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struct device_operations pmc_ops = {
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.read_resources = soc_pmc_read_resources,
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.set_resources = noop_set_resources,
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.init = soc_acpi_mode_init,
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.enable = pmc_init,
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_fill_ssdt = soc_pmc_fill_ssdt,
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