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soc/intel/common/gpio: Add PAD_NC_LOCK and PAD_CFG_GPI_SCI_LOCK macro 

Add PAD_NC_LOCK and PAD_CFG_GPI_SCI_LOCK macro to support mainboard
to lock NC and GPI_SCI pins as applicable.

BUG=b:216583542
TEST=build passed

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61655
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Eric Lai 2022-02-07 12:16:28 +08:00 committed by Felix Held
parent 7d7f3ae69b
commit 9f9d5106c5
1 changed files with 15 additions and 0 deletions
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15
src/soc/intel/common/block/include/intelblocks/gpio_defs.h
View File

@ -364,6 +364,14 @@
PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \
PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
/* No Connect configuration with lock */
#define PAD_NC_LOCK(pad, pull, lock_action) \
_PAD_CFG_STRUCT_LOCK(pad, \
PAD_RESET(PWROK) | PAD_FUNC(GPIO) | \
PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \
PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \
PAD_LOCK(lock_action))
/* General purpose input, routed to APIC */
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
_PAD_CFG_STRUCT(pad, \
@ -427,6 +435,13 @@
PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
PAD_IOSSTATE(TxDRxE))
/* General purpose input with lock, routed to SCI */
#define PAD_CFG_GPI_SCI_LOCK(pad, pull, trig, inv, lock_action) \
_PAD_CFG_STRUCT_LOCK(pad, \
PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE) | \
PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
PAD_IOSSTATE(TxDRxE), PAD_LOCK(lock_action))
/* General purpose input, routed to SCI */
#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
_PAD_CFG_STRUCT(pad, \