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drivers/aspeed: Add AST2500 support 

Tested on AST2500.
Code for AST2400 still works.

Copy code from GNU/Linux kernel to coreboot to add AST2500 support.

Change-Id: I25bd34dd52a0acd3e04fc5818e011215ef907fad
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This commit is contained in:
Patrick Rudolph 2019-08-05 10:43:09 +02:00 committed by Philipp Deppenwiese
parent f1a4ae0a48
commit 9fe3d692c7
5 changed files with 553 additions and 84 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/drivers/aspeed/common/ast_dp501.c
View File

@ -147,7 +147,7 @@ bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size)
return false; return false;
} }
bool ast_launch_m68k(struct drm_device *dev) static bool ast_launch_m68k(struct drm_device *dev)
{ {
struct ast_private *ast = dev->dev_private; struct ast_private *ast = dev->dev_private;
u32 i, data, len = 0; u32 i, data, len = 0;
@ -161,7 +161,10 @@ bool ast_launch_m68k(struct drm_device *dev)
if (ast->dp501_fw_addr) { if (ast->dp501_fw_addr) {
fw_addr = ast->dp501_fw_addr; fw_addr = ast->dp501_fw_addr;
len = 32*1024; len = 32*1024;
} else if (ast->dp501_fw) { } else {
if (!ast->dp501_fw)
return false;
fw_addr = (u8 *)ast->dp501_fw->data; fw_addr = (u8 *)ast->dp501_fw->data;
len = ast->dp501_fw->size; len = ast->dp501_fw->size;
} }
@ -226,11 +229,7 @@ u8 ast_get_dp501_max_clk(struct drm_device *dev)
/* Read Link Capability */ /* Read Link Capability */
offset = 0xf014; offset = 0xf014;
data = ast_mindwm(ast, boot_address + offset); *(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
linkcap[0] = (data & 0xff000000) >> 24;
linkcap[1] = (data & 0x00ff0000) >> 16;
linkcap[2] = (data & 0x0000ff00) >> 8;
linkcap[3] = (data & 0x000000ff);
if (linkcap[2] == 0) { if (linkcap[2] == 0) {
linkrate = linkcap[0]; linkrate = linkcap[0];
linklanes = linkcap[1]; linklanes = linkcap[1];

62
src/drivers/aspeed/common/ast_dram_tables.h
View File

@ -159,4 +159,66 @@ static const struct ast_dramstruct ast2100_dram_table_data[] = {
{ 0xffff, 0xffffffff }, { 0xffff, 0xffffffff },
}; };
/*
* AST2500 DRAM settings modules
*/
#define REGTBL_NUM 17
#define REGIDX_010 0
#define REGIDX_014 1
#define REGIDX_018 2
#define REGIDX_020 3
#define REGIDX_024 4
#define REGIDX_02C 5
#define REGIDX_030 6
#define REGIDX_214 7
#define REGIDX_2E0 8
#define REGIDX_2E4 9
#define REGIDX_2E8 10
#define REGIDX_2EC 11
#define REGIDX_2F0 12
#define REGIDX_2F4 13
#define REGIDX_2F8 14
#define REGIDX_RFC 15
#define REGIDX_PLL 16
static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
0x64604D38, /* 0x010 */
0x29690599, /* 0x014 */
0x00000300, /* 0x018 */
0x00000000, /* 0x020 */
0x00000000, /* 0x024 */
0x02181E70, /* 0x02C */
0x00000040, /* 0x030 */
0x00000024, /* 0x214 */
0x02001300, /* 0x2E0 */
0x0E0000A0, /* 0x2E4 */
0x000E001B, /* 0x2E8 */
0x35B8C105, /* 0x2EC */
0x08090408, /* 0x2F0 */
0x9B000800, /* 0x2F4 */
0x0E400A00, /* 0x2F8 */
0x9971452F, /* tRFC */
0x000071C1 /* PLL */
};
static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
0x63604E37, /* 0x010 */
0xE97AFA99, /* 0x014 */
0x00019000, /* 0x018 */
0x08000000, /* 0x020 */
0x00000400, /* 0x024 */
0x00000410, /* 0x02C */
0x00000101, /* 0x030 */
0x00000024, /* 0x214 */
0x03002900, /* 0x2E0 */
0x0E0000A0, /* 0x2E4 */
0x000E001C, /* 0x2E8 */
0x35B8C106, /* 0x2EC */
0x08080607, /* 0x2F0 */
0x9B000900, /* 0x2F4 */
0x0E400A00, /* 0x2F8 */
0x99714545, /* tRFC */
0x000071C1 /* PLL */
};
#endif #endif

4
src/drivers/aspeed/common/ast_drv.h
View File

@ -63,6 +63,7 @@ enum ast_tx_chip {
#define AST_DRAM_1Gx32 3 #define AST_DRAM_1Gx32 3
#define AST_DRAM_2Gx16 6 #define AST_DRAM_2Gx16 6
#define AST_DRAM_4Gx16 7 #define AST_DRAM_4Gx16 7
#define AST_DRAM_8Gx16 8
struct ast_fbdev; struct ast_fbdev;
@ -311,13 +312,12 @@ void ast_post_gpu(struct drm_device *dev);
u32 ast_mindwm(struct ast_private *ast, u32 r); u32 ast_mindwm(struct ast_private *ast, u32 r);
void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
/* ast dp501 */ /* ast dp501 */
int ast_load_dp501_microcode(struct drm_device *dev);
void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
bool ast_launch_m68k(struct drm_device *dev);
bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
u8 ast_get_dp501_max_clk(struct drm_device *dev); u8 ast_get_dp501_max_clk(struct drm_device *dev);
void ast_init_3rdtx(struct drm_device *dev); void ast_init_3rdtx(struct drm_device *dev);
void ast_release_firmware(struct drm_device *dev);
/* ast mode */ /* ast mode */
int ast_crtc_mode_set(struct drm_crtc *crtc, int ast_crtc_mode_set(struct drm_crtc *crtc,

26
src/drivers/aspeed/common/ast_main.c
View File

@ -75,8 +75,10 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
} else { } else {
pci_read_config_dword(ast->dev->pdev, 0x08, &data); pci_read_config_dword(ast->dev->pdev, 0x08, &data);
uint8_t revision = data & 0xff; uint8_t revision = data & 0xff;
if (revision >= 0x40) {
if (revision >= 0x30) { ast->chip = AST2500;
DRM_INFO("AST 2500 detected\n");
} else if (revision >= 0x30) {
ast->chip = AST2400; ast->chip = AST2400;
DRM_INFO("AST 2400 detected\n"); DRM_INFO("AST 2400 detected\n");
} else if (revision >= 0x20) { } else if (revision >= 0x20) {
@ -151,6 +153,8 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
ast->support_wide_screen = true; ast->support_wide_screen = true;
if (ast->chip == AST2400 && data == 0x100) /* ast1400 */ if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
ast->support_wide_screen = true; ast->support_wide_screen = true;
if (ast->chip == AST2500 && data == 0x100) /* ast2510 */
ast->support_wide_screen = true;
} }
break; break;
} }
@ -241,7 +245,23 @@ static int ast_get_dram_info(struct drm_device *dev)
else else
ast->dram_bus_width = 32; ast->dram_bus_width = 32;
if (ast->chip == AST2300 || ast->chip == AST2400) { if (ast->chip == AST2500) {
switch (data & 0x03) {
case 0:
ast->dram_type = AST_DRAM_1Gx16;
break;
default:
case 1:
ast->dram_type = AST_DRAM_2Gx16;
break;
case 2:
ast->dram_type = AST_DRAM_4Gx16;
break;
case 3:
ast->dram_type = AST_DRAM_8Gx16;
break;
}
} else if (ast->chip == AST2300 || ast->chip == AST2400) {
switch (data & 0x03) { switch (data & 0x03) {
case 0: case 0:
ast->dram_type = AST_DRAM_512Mx16; ast->dram_type = AST_DRAM_512Mx16;

532
src/drivers/aspeed/common/ast_post.c
View File

@ -33,7 +33,8 @@
#include "ast_drv.h" #include "ast_drv.h"
#include "ast_dram_tables.h" #include "ast_dram_tables.h"
static void ast_init_dram_2300(struct drm_device *dev); static void ast_post_chip_2300(struct drm_device *dev);
static void ast_post_chip_2500(struct drm_device *dev);
void ast_enable_vga(struct drm_device *dev) void ast_enable_vga(struct drm_device *dev)
{ {
@ -60,13 +61,9 @@ bool ast_is_vga_enabled(struct drm_device *dev)
/* TODO 1180 */ /* TODO 1180 */
} else { } else {
ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
if (ch) { return !!(ch & 0x01);
ast_open_key(ast);
ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff);
return ch & 0x04;
} }
} return false;
return 0;
} }
static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
@ -85,10 +82,11 @@ ast_set_def_ext_reg(struct drm_device *dev)
uint8_t revision = data & 0xff; uint8_t revision = data & 0xff;
/* reset scratch */ /* reset scratch */
for (i = 0x81; i <= 0x8f; i++) for (i = 0x81; i <= 0x9f; i++)
ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
if (ast->chip == AST2300 || ast->chip == AST2400) { if (ast->chip == AST2300 || ast->chip == AST2400 ||
ast->chip == AST2500) {
if (revision >= 0x20) if (revision >= 0x20)
ext_reg_info = extreginfo_ast2300; ext_reg_info = extreginfo_ast2300;
else else
@ -112,7 +110,8 @@ ast_set_def_ext_reg(struct drm_device *dev)
/* Enable RAMDAC for A1 */ /* Enable RAMDAC for A1 */
reg = 0x04; reg = 0x04;
if (ast->chip == AST2300 || ast->chip == AST2400) if (ast->chip == AST2300 || ast->chip == AST2400 ||
ast->chip == AST2500)
reg |= 0x20; reg |= 0x20;
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
} }
@ -393,12 +392,14 @@ void ast_post_gpu(struct drm_device *dev)
pci_write_config_dword(ast->dev->pdev, 0x04, reg); pci_write_config_dword(ast->dev->pdev, 0x04, reg);
ast_enable_vga(dev); ast_enable_vga(dev);
ast_enable_mmio(dev);
ast_open_key(ast); ast_open_key(ast);
ast_enable_mmio(dev);
ast_set_def_ext_reg(dev); ast_set_def_ext_reg(dev);
if (ast->chip == AST2300 || ast->chip == AST2400) if (ast->chip == AST2500)
ast_init_dram_2300(dev); ast_post_chip_2500(dev);
else if (ast->chip == AST2300 || ast->chip == AST2400)
ast_post_chip_2300(dev);
else else
ast_init_dram_reg(dev); ast_init_dram_reg(dev);
@ -458,87 +459,72 @@ static const u32 pattern[8] = {
0x7C61D253 0x7C61D253
}; };
static int mmc_test_burst(struct ast_private *ast, u32 datagen) static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
{ {
u32 data, timeout; u32 data, timeout;
ast_moutdwm(ast, 0x1e6e0070, 0x00000000); ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3)); ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
timeout = 0;
do {
data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
if (data & 0x2000) {
return 0;
}
if (++timeout > TIMEOUT) {
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
return 0;
}
} while (!data);
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
return 1;
}
static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
{
u32 data, timeout;
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
timeout = 0;
do {
data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
if (++timeout > TIMEOUT) {
ast_moutdwm(ast, 0x1e6e0070, 0x0);
return -1;
}
} while (!data);
data = ast_mindwm(ast, 0x1e6e0078);
data = (data | (data >> 16)) & 0xffff;
ast_moutdwm(ast, 0x1e6e0070, 0x0);
return data;
}
static int mmc_test_single(struct ast_private *ast, u32 datagen)
{
u32 data, timeout;
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
timeout = 0; timeout = 0;
do { do {
data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
if (data & 0x2000) if (data & 0x2000)
return 0; return false;
if (++timeout > TIMEOUT) { if (++timeout > TIMEOUT) {
ast_moutdwm(ast, 0x1e6e0070, 0x0); ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
return 0; return false;
} }
} while (!data); } while (!data);
ast_moutdwm(ast, 0x1e6e0070, 0x0); ast_moutdwm(ast, 0x1e6e0070, 0x0);
return 1; return true;
} }
static int mmc_test_single2(struct ast_private *ast, u32 datagen) static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
{ {
u32 data, timeout; u32 data, timeout;
ast_moutdwm(ast, 0x1e6e0070, 0x00000000); ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
timeout = 0; timeout = 0;
do { do {
data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
if (++timeout > TIMEOUT) { if (++timeout > TIMEOUT) {
ast_moutdwm(ast, 0x1e6e0070, 0x0); ast_moutdwm(ast, 0x1e6e0070, 0x0);
return -1; return 0xffffffff;
} }
} while (!data); } while (!data);
data = ast_mindwm(ast, 0x1e6e0078); data = ast_mindwm(ast, 0x1e6e0078);
data = (data | (data >> 16)) & 0xffff; data = (data | (data >> 16)) & 0xffff;
ast_moutdwm(ast, 0x1e6e0070, 0x0); ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
return data; return data;
} }
static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
{
return mmc_test(ast, datagen, 0xc1);
}
static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
{
return mmc_test2(ast, datagen, 0x41);
}
static bool mmc_test_single(struct ast_private *ast, u32 datagen)
{
return mmc_test(ast, datagen, 0xc5);
}
static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
{
return mmc_test2(ast, datagen, 0x05);
}
static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
{
return mmc_test(ast, datagen, 0x85);
}
static int cbr_test(struct ast_private *ast) static int cbr_test(struct ast_private *ast)
{ {
u32 data; u32 data;
@ -614,16 +600,16 @@ static u32 cbr_scan2(struct ast_private *ast)
return data2; return data2;
} }
static u32 cbr_test3(struct ast_private *ast) static bool cbr_test3(struct ast_private *ast)
{ {
if (!mmc_test_burst(ast, 0)) if (!mmc_test_burst(ast, 0))
return 0; return false;
if (!mmc_test_single(ast, 0)) if (!mmc_test_single(ast, 0))
return 0; return false;
return 1; return true;
} }
static u32 cbr_scan3(struct ast_private *ast) static bool cbr_scan3(struct ast_private *ast)
{ {
u32 patcnt, loop; u32 patcnt, loop;
@ -634,9 +620,9 @@ static u32 cbr_scan3(struct ast_private *ast)
break; break;
} }
if (loop == 2) if (loop == 2)
return 0; return false;
} }
return 1; return true;
} }
static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param) static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
@ -1660,7 +1646,7 @@ ddr2_init_start:
} }
static void ast_init_dram_2300(struct drm_device *dev) static void ast_post_chip_2300(struct drm_device *dev)
{ {
struct ast_private *ast = dev->dev_private; struct ast_private *ast = dev->dev_private;
struct ast2300_dram_param param; struct ast2300_dram_param param;
@ -1753,3 +1739,405 @@ static void ast_init_dram_2300(struct drm_device *dev)
if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT)
dev_err(dev->pdev, "Timeout while waiting for register\n"); dev_err(dev->pdev, "Timeout while waiting for register\n");
} }
static bool cbr_test_2500(struct ast_private *ast)
{
ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
if (!mmc_test_burst(ast, 0))
return false;
if (!mmc_test_single_2500(ast, 0))
return false;
return true;
}
static bool ddr_test_2500(struct ast_private *ast)
{
ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
if (!mmc_test_burst(ast, 0))
return false;
if (!mmc_test_burst(ast, 1))
return false;
if (!mmc_test_burst(ast, 2))
return false;
if (!mmc_test_burst(ast, 3))
return false;
if (!mmc_test_single_2500(ast, 0))
return false;
return true;
}
static void ddr_init_common_2500(struct ast_private *ast)
{
ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
}
static void ddr_phy_init_2500(struct ast_private *ast)
{
u32 data, pass, timecnt;
pass = 0;
ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
while (!pass) {
for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
if (!data)
break;
}
if (timecnt != TIMEOUT) {
data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
if (!data)
pass = 1;
}
if (!pass) {
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
udelay(10); /* delay 10 us */
ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
}
}
ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
}
/*
* Check DRAM Size
* 1Gb : 0x80000000 ~ 0x87FFFFFF
* 2Gb : 0x80000000 ~ 0x8FFFFFFF
* 4Gb : 0x80000000 ~ 0x9FFFFFFF
* 8Gb : 0x80000000 ~ 0xBFFFFFFF
*/
static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
{
u32 reg_04, reg_14;
reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
ast_moutdwm(ast, 0xA0100000, 0x41424344);
ast_moutdwm(ast, 0x90100000, 0x35363738);
ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
/* Check 8Gbit */
if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
reg_04 |= 0x03;
reg_14 |= (tRFC >> 24) & 0xFF;
/* Check 4Gbit */
} else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
reg_04 |= 0x02;
reg_14 |= (tRFC >> 16) & 0xFF;
/* Check 2Gbit */
} else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
reg_04 |= 0x01;
reg_14 |= (tRFC >> 8) & 0xFF;
} else {
reg_14 |= tRFC & 0xFF;
}
ast_moutdwm(ast, 0x1E6E0004, reg_04);
ast_moutdwm(ast, 0x1E6E0014, reg_14);
}
static void enable_cache_2500(struct ast_private *ast)
{
u32 reg_04, data;
reg_04 = ast_mindwm(ast, 0x1E6E0004);
ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
do
data = ast_mindwm(ast, 0x1E6E0004);
while (!(data & 0x80000));
ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
}
static void set_mpll_2500(struct ast_private *ast)
{
u32 addr, data, param;
/* Reset MMC */
ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
ast_moutdwm(ast, addr, 0x0);
addr += 4;
}
ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
if (data) {
/* CLKIN = 25MHz */
param = 0x930023E0;
ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
} else {
/* CLKIN = 24MHz */
param = 0x93002400;
}
ast_moutdwm(ast, 0x1E6E2020, param);
udelay(100);
}
static void reset_mmc_2500(struct ast_private *ast)
{
ast_moutdwm(ast, 0x1E78505C, 0x00000004);
ast_moutdwm(ast, 0x1E785044, 0x00000001);
ast_moutdwm(ast, 0x1E785048, 0x00004755);
ast_moutdwm(ast, 0x1E78504C, 0x00000013);
mdelay(100);
ast_moutdwm(ast, 0x1E785054, 0x00000077);
ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
}
static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
{
ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
/* DDR PHY Setting */
ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
/* Controller Setting */
ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
/* Wait DDR PHY init done */
ddr_phy_init_2500(ast);
ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
enable_cache_2500(ast);
ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
}
static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
{
u32 data, data2, pass, retrycnt;
u32 ddr_vref, phy_vref;
u32 min_ddr_vref = 0, min_phy_vref = 0;
u32 max_ddr_vref = 0, max_phy_vref = 0;
ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
/* DDR PHY Setting */
ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
/* Controller Setting */
ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
/* Train PHY Vref first */
pass = 0;
for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
max_phy_vref = 0x0;
pass = 0;
ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
/* Fire DFI Init */
ddr_phy_init_2500(ast);
ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
if (cbr_test_2500(ast)) {
pass++;
data = ast_mindwm(ast, 0x1E6E03D0);
data2 = data >> 8;
data = data & 0xff;
if (data > data2)
data = data2;
if (max_phy_vref < data) {
max_phy_vref = data;
min_phy_vref = phy_vref;
}
} else if (pass > 0)
break;
}
}
ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
/* Train DDR Vref next */
pass = 0;
for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
min_ddr_vref = 0xFF;
max_ddr_vref = 0x0;
pass = 0;
for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
/* Fire DFI Init */
ddr_phy_init_2500(ast);
ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
if (cbr_test_2500(ast)) {
pass++;
if (min_ddr_vref > ddr_vref)
min_ddr_vref = ddr_vref;
if (max_ddr_vref < ddr_vref)
max_ddr_vref = ddr_vref;
} else if (pass != 0)
break;
}
}
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
/* Wait DDR PHY init done */
ddr_phy_init_2500(ast);
ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
enable_cache_2500(ast);
ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
}
static bool ast_dram_init_2500(struct ast_private *ast)
{
u32 data;
u32 max_tries = 5;
do {
if (max_tries-- == 0)
return false;
set_mpll_2500(ast);
reset_mmc_2500(ast);
ddr_init_common_2500(ast);
data = ast_mindwm(ast, 0x1E6E2070);
if (data & 0x01000000)
ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
else
ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
} while (!ddr_test_2500(ast));
ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
/* Patch code */
data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
return true;
}
void ast_post_chip_2500(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
u32 temp;
u8 reg;
reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
if ((reg & 0x80) == 0) {/* vga only */
/* Clear bus lock condition */
ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
ast_moutdwm(ast, 0x1e600084, 0x00010000);
ast_moutdwm(ast, 0x1e600088, 0x00000000);
ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
ast_write32(ast, 0xf004, 0x1e6e0000);
ast_write32(ast, 0xf000, 0x1);
ast_write32(ast, 0x12000, 0x1688a8a8);
while (ast_read32(ast, 0x12000) != 0x1)
;
ast_write32(ast, 0x10000, 0xfc600309);
while (ast_read32(ast, 0x10000) != 0x1)
;
/* Slow down CPU/AHB CLK in VGA only mode */
temp = ast_read32(ast, 0x12008);
temp |= 0x73;
ast_write32(ast, 0x12008, temp);
/* Reset USB port to patch USB unknown device issue */
ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
temp = ast_mindwm(ast, 0x1e6e2094);
temp |= 0x00004000;
ast_moutdwm(ast, 0x1e6e2094, temp);
temp = ast_mindwm(ast, 0x1e6e2070);
if (temp & 0x00800000) {
ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
mdelay(100);
ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
}
if (!ast_dram_init_2500(ast))
printk(BIOS_ERR, "AST: DRAM init failed !\n");
temp = ast_mindwm(ast, 0x1e6e2040);
ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
}
/* wait ready */
do {
reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
} while ((reg & 0x40) == 0);
}