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coreboot used to have two different "APIs" for memory accesses: 

read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)

read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.

This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-01-16 17:53:38 +00:00 committed by Stefan Reinauer
parent 984e0f3a0c
commit 9fe4d797a3
32 changed files with 264 additions and 219 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
src/arch/i386/include/arch/io.h
View File

@ -136,6 +136,14 @@ static inline void insl(uint16_t port, void *addr, unsigned long count)
);
}
/* XXX XXX XXX This is a story from the evil API from hell XXX XXX XXX
* We have different functions for memory access in pre-ram stage and ram
* stage. Those in pre-ram stage are called write32 and expect the address
* first and the address as a pointer type. Those in ram stage are called
* writel and expect the datum first and the address as an integer type.
* Until all code is checked and fixed, I'll add both versions here now.
*/
static inline void writeb(uint8_t b, volatile void *addr)
{
*(volatile uint8_t *) addr = b;
@ -166,5 +174,37 @@ static inline uint32_t readl(const volatile void *addr)
return *(volatile uint32_t *) addr;
}
#if !defined(__PRE_RAM__)
static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
{
return *((volatile uint8_t *)(addr));
}
static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr)
{
return *((volatile uint16_t *)(addr));
}
static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr)
{
return *((volatile uint32_t *)(addr));
}
static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value)
{
*((volatile uint8_t *)(addr)) = value;
}
static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value)
{
*((volatile uint16_t *)(addr)) = value;
}
static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value)
{
*((volatile uint32_t *)(addr)) = value;
}
#endif
#endif

3
src/arch/i386/include/arch/romcc_io.h
View File

@ -3,7 +3,7 @@
#include <stdint.h>
#ifdef __PRE_RAM__
static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
{
return *((volatile uint8_t *)(addr));
@ -33,6 +33,7 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui
{
*((volatile uint32_t *)(addr)) = value;
}
#endif
#if CONFIG_MMCONF_SUPPORT

2
src/arch/i386/lib/console.c
View File

@ -10,7 +10,7 @@
#define COREBOOT_EXTRA_VERSION ""
#endif
static void console_init(void)
void console_init(void)
{
static const char console_test[] =
"\r\n\r\ncoreboot-"

4
src/arch/i386/lib/printk_init.c
View File

@ -18,6 +18,7 @@
*/
#include <stdarg.h>
#include <console/console.h>
#include <console/vtxprintf.h>
#include <console/loglevel.h>
#include <uart8250.h>
@ -32,9 +33,6 @@ int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL
#endif
void console_tx_byte(unsigned char byte);
int do_printk(int msg_level, const char *fmt, ...);
void console_tx_byte(unsigned char byte)
{
if (byte == '\n')

92
src/lib/usbdebug_direct.c
View File

@ -83,7 +83,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
unsigned ctrl;
int loop = 0x100000;
do {
ctrl = readl(&ehci_debug->control);
ctrl = read32(&ehci_debug->control);
/* Stop when the transaction is finished */
if (ctrl & DBGP_DONE)
break;
@ -94,7 +94,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
/* Now that we have observed the completed transaction,
* clear the done bit.
*/
writel(ctrl | DBGP_DONE, &ehci_debug->control);
write32(&ehci_debug->control, ctrl | DBGP_DONE);
return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
}
@ -119,9 +119,9 @@ static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, unsigned ctrl)
int loop = 3;
retry:
writel(ctrl | DBGP_GO, &ehci_debug->control);
write32(&ehci_debug->control, ctrl | DBGP_GO);
ret = dbgp_wait_until_complete(ehci_debug);
pids = readl(&ehci_debug->pids);
pids = read32(&ehci_debug->pids);
lpid = DBGP_PID_GET(pids);
if (ret < 0)
@ -151,8 +151,8 @@ static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int
lo |= bytes[i] << (8*i);
for (; i < 8 && i < size; i++)
hi |= bytes[i] << (8*(i - 4));
writel(lo, &ehci_debug->data03);
writel(hi, &ehci_debug->data47);
write32(&ehci_debug->data03, lo);
write32(&ehci_debug->data47, hi);
}
static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
@ -160,8 +160,8 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
unsigned char *bytes = buf;
unsigned lo, hi;
int i;
lo = readl(&ehci_debug->data03);
hi = readl(&ehci_debug->data47);
lo = read32(&ehci_debug->data03);
hi = read32(&ehci_debug->data47);
for (i = 0; i < 4 && i < size; i++)
bytes[i] = (lo >> (8*i)) & 0xff;
for (; i < 8 && i < size; i++)
@ -177,17 +177,17 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, unsigned devnum, un
addr = DBGP_EPADDR(devnum, endpoint);
pids = readl(&ehci_debug->pids);
pids = read32(&ehci_debug->pids);
pids = DBGP_PID_UPDATE(pids, USB_PID_OUT);
ctrl = readl(&ehci_debug->control);
ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, size);
ctrl |= DBGP_OUT;
ctrl |= DBGP_GO;
dbgp_set_data(ehci_debug, bytes, size);
writel(addr, &ehci_debug->address);
writel(pids, &ehci_debug->pids);
write32(&ehci_debug->address, addr);
write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, ctrl);
if (ret < 0) {
@ -211,16 +211,16 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum, uns
addr = DBGP_EPADDR(devnum, endpoint);
pids = readl(&ehci_debug->pids);
pids = read32(&ehci_debug->pids);
pids = DBGP_PID_UPDATE(pids, USB_PID_IN);
ctrl = readl(&ehci_debug->control);
ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, size);
ctrl &= ~DBGP_OUT;
ctrl |= DBGP_GO;
writel(addr, &ehci_debug->address);
writel(pids, &ehci_debug->pids);
write32(&ehci_debug->address, addr);
write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, ctrl);
if (ret < 0)
return ret;
@ -256,15 +256,15 @@ static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, i
pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
addr = DBGP_EPADDR(devnum, 0);
ctrl = readl(&ehci_debug->control);
ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
ctrl |= DBGP_OUT;
ctrl |= DBGP_GO;
/* Send the setup message */
dbgp_set_data(ehci_debug, &req, sizeof(req));
writel(addr, &ehci_debug->address);
writel(pids, &ehci_debug->pids);
write32(&ehci_debug->address, addr);
write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, ctrl);
if (ret < 0)
return ret;
@ -282,25 +282,25 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
int loop;
/* Reset the usb debug port */
portsc = readl(&ehci_regs->port_status[port - 1]);
portsc = read32(&ehci_regs->port_status[port - 1]);
portsc &= ~PORT_PE;
portsc |= PORT_RESET;
writel(portsc, &ehci_regs->port_status[port - 1]);
write32(&ehci_regs->port_status[port - 1], portsc);
delay = HUB_ROOT_RESET_TIME;
for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
delay_time += delay) {
dbgp_mdelay(delay);
portsc = readl(&ehci_regs->port_status[port - 1]);
portsc = read32(&ehci_regs->port_status[port - 1]);
if (portsc & PORT_RESET) {
/* force reset to complete */
loop = 2;
writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
&ehci_regs->port_status[port - 1]);
write32(&ehci_regs->port_status[port - 1],
portsc & ~(PORT_RWC_BITS | PORT_RESET));
do {
dbgp_mdelay(delay);
portsc = readl(&ehci_regs->port_status[port - 1]);
portsc = read32(&ehci_regs->port_status[port - 1]);
delay_time += delay;
} while ((portsc & PORT_RESET) && (--loop > 0));
if (!loop) {
@ -329,7 +329,7 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
int ret, reps;
for (reps = 0; reps < 3; reps++) {
dbgp_mdelay(100);
status = readl(&ehci_regs->status);
status = read32(&ehci_regs->status);
if (status & STS_PCD) {
ret = ehci_reset_port(ehci_regs, port);
if (ret == 0)
@ -366,7 +366,7 @@ static void usbdebug_direct_init(unsigned ehci_bar, unsigned offset, struct ehci
unsigned playtimes = 3;
ehci_caps = (struct ehci_caps *)ehci_bar;
ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase)));
ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(read32(&ehci_caps->hc_capbase)));
ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
info->ehci_debug = (void *)0;
@ -375,7 +375,7 @@ try_next_time:
port_map_tried = 0;
try_next_port:
hcs_params = readl(&ehci_caps->hcs_params);
hcs_params = read32(&ehci_caps->hcs_params);
debug_port = HCS_DEBUG_PORT(hcs_params);
n_ports = HCS_N_PORTS(hcs_params);
@ -385,7 +385,7 @@ try_next_port:
#if 1
for (i = 1; i <= n_ports; i++) {
portsc = readl(&ehci_regs->port_status[i-1]);
portsc = read32(&ehci_regs->port_status[i-1]);
dbgp_printk("PORTSC #%d: %08x\n", i, portsc);
}
#endif
@ -400,11 +400,11 @@ try_next_port:
/* Reset the EHCI controller */
loop = 10;
cmd = readl(&ehci_regs->command);
cmd = read32(&ehci_regs->command);
cmd |= CMD_RESET;
writel(cmd, &ehci_regs->command);
write32(&ehci_regs->command, cmd);
do {
cmd = readl(&ehci_regs->command);
cmd = read32(&ehci_regs->command);
} while ((cmd & CMD_RESET) && (--loop > 0));
if(!loop)
@ -413,24 +413,24 @@ try_next_port:
dbgp_printk("EHCI controller reset successfully.\n");
/* Claim ownership, but do not enable yet */
ctrl = readl(&ehci_debug->control);
ctrl = read32(&ehci_debug->control);
ctrl |= DBGP_OWNER;
ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
writel(ctrl, &ehci_debug->control);
write32(&ehci_debug->control, ctrl);
/* Start the ehci running */
cmd = readl(&ehci_regs->command);
cmd = read32(&ehci_regs->command);
cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
cmd |= CMD_RUN;
writel(cmd, &ehci_regs->command);
write32(&ehci_regs->command, cmd);
/* Ensure everything is routed to the EHCI */
writel(FLAG_CF, &ehci_regs->configured_flag);
write32(&ehci_regs->configured_flag, FLAG_CF);
/* Wait until the controller is no longer halted */
loop = 10;
do {
status = readl(&ehci_regs->status);
status = read32(&ehci_regs->status);
} while ((status & STS_HALT) && (--loop>0));
if(!loop) {
@ -448,21 +448,21 @@ try_next_port:
dbgp_printk("EHCI done waiting for port.\n");
/* Enable the debug port */
ctrl = readl(&ehci_debug->control);
ctrl = read32(&ehci_debug->control);
ctrl |= DBGP_CLAIM;
writel(ctrl, &ehci_debug->control);
ctrl = readl(&ehci_debug->control);
write32(&ehci_debug->control, ctrl);
ctrl = read32(&ehci_debug->control);
if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
dbgp_printk("No device in EHCI debug port.\n");
writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control);
write32(&ehci_debug->control, ctrl & ~DBGP_CLAIM);
goto err;
}
dbgp_printk("EHCI debug port enabled.\n");
/* Completely transfer the debug device to the debug controller */
portsc = readl(&ehci_regs->port_status[debug_port - 1]);
portsc = read32(&ehci_regs->port_status[debug_port - 1]);
portsc &= ~PORT_PE;
writel(portsc, &ehci_regs->port_status[debug_port - 1]);
write32(&ehci_regs->port_status[debug_port - 1], portsc);
dbgp_mdelay(100);
@ -529,9 +529,9 @@ try_next_port:
return;
err:
/* Things didn't work so remove my claim */
ctrl = readl(&ehci_debug->control);
ctrl = read32(&ehci_debug->control);
ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
writel(ctrl, &ehci_debug->control);
write32(&ehci_debug->control, ctrl);
next_debug_port:
port_map_tried |= (1<<(debug_port-1));

1
src/mainboard/amd/db800/cache_as_ram_auto.c
View File

@ -19,6 +19,7 @@
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#include <stdint.h>
#include <device/pci_def.h>

1
src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c
View File

@ -19,6 +19,7 @@
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#include <stdint.h>
#include <device/pci_def.h>

1
src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c
View File

@ -1,4 +1,5 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#include <stdint.h>
#include <device/pci_def.h>

1
src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c
View File

@ -19,6 +19,7 @@
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#include <stdint.h>
#include <device/pci_def.h>

22
src/mainboard/intel/eagleheights/auto.c
View File

@ -133,22 +133,22 @@ void early_config(void) {
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
/* Disable watchdog */
gcs = readl(DEFAULT_RCBA + RCBA_GCS);
gcs = read32(DEFAULT_RCBA + RCBA_GCS);
gcs |= (1 << 5); /* No reset */
writel(gcs, DEFAULT_RCBA + RCBA_GCS);
write32(DEFAULT_RCBA + RCBA_GCS, gcs);
/* Configure PCIe port B as 4x */
rpc = readl(DEFAULT_RCBA + RCBA_RPC);
rpc = read32(DEFAULT_RCBA + RCBA_RPC);
rpc |= (3 << 0);
writel(rpc, DEFAULT_RCBA + RCBA_RPC);
write32(DEFAULT_RCBA + RCBA_RPC, rpc);
/* Disable Modem, Audio, PCIe ports 2/3/4 */
fd = readl(DEFAULT_RCBA + RCBA_FD);
fd = read32(DEFAULT_RCBA + RCBA_FD);
fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
writel(fd, DEFAULT_RCBA + RCBA_FD);
write32(DEFAULT_RCBA + RCBA_FD, fd);
/* Enable HPET */
writel((1 << 7), DEFAULT_RCBA + RCBA_HPTC);
write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
/* Improve interrupt routing
* D31:F2 SATA INTB# -> PIRQD
@ -160,10 +160,10 @@ void early_config(void) {
* D28:F0 PCIe Port 1 INTA# -> PIRQE
*/
writew(0x0230, DEFAULT_RCBA + RCBA_D31IR);
writew(0x3210, DEFAULT_RCBA + RCBA_D30IR);
writew(0x3237, DEFAULT_RCBA + RCBA_D29IR);
writew(0x3214, DEFAULT_RCBA + RCBA_D28IR);
write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230);
write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210);
write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237);
write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214);
/* Setup sata mode */
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));

16
src/mainboard/intel/eagleheights/mptable.c
View File

@ -234,10 +234,10 @@ void *smp_write_config_table(void *v)
/* PCIe Port B
*/
for(i = 0; i < 4; i++) {
pin = (readl(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
route = PIRQ_A + ((readw(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
}
}
@ -245,20 +245,20 @@ void *smp_write_config_table(void *v)
/* USB 1.1 : device 29, function 0, 1
*/
for(i = 0; i < 2; i++) {
pin = (readl(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
}
}
/* USB 2.0 : device 29, function 7
*/
pin = (readl(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
pin = (read32(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
}
@ -267,10 +267,10 @@ void *smp_write_config_table(void *v)
Performance counters : device 31 function 4
*/
for(i = 2; i < 5; i++) {
pin = (readl(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
route = PIRQ_A + ((readw(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
}
}

1
src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
View File

@ -22,6 +22,7 @@
/* Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. */
#define ASSEMBLY 1
#define __PRE_RAM__
#include <stdlib.h>
#include <stdint.h>

1
src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c
View File

@ -22,6 +22,7 @@
/* Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. */
#define ASSEMBLY 1
#define __PRE_RAM__
#include <stdlib.h>
#include <stdint.h>

1
src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
View File

@ -18,6 +18,7 @@
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#include <stdint.h>
#include <spd.h>

4
src/northbridge/amd/gx1/northbridge.c
View File

@ -36,8 +36,8 @@ static void optimize_xbus(device_t dev)
static void enable_shadow(device_t dev)
{
writel(0x77777777,GX_BASE+BC_XMAP_2);
writel(0x77777777,GX_BASE+BC_XMAP_3);
write32(GX_BASE+BC_XMAP_2, 0x77777777);
write32(GX_BASE+BC_XMAP_3, 0x77777777);
}
static void northbridge_init(device_t dev)

4
src/northbridge/amd/gx1/raminit.c
View File

@ -34,12 +34,12 @@ it with the version available from LANL.
void setGX1Mem(unsigned int addr, unsigned int data)
{
writel(data, (volatile void *)addr);
write32(addr, data);
}
unsigned int getGX1Mem(unsigned int addr)
{
return (unsigned int)readl((const volatile void *)addr);
return (unsigned int)read32(addr);
}
void do_refresh(void)

6
src/southbridge/amd/amd8111/amd8111_nic.c
View File

@ -54,12 +54,12 @@ static void nic_init(struct device *dev)
/* Hard Reset PHY */
printk_debug("Reseting PHY... ");
if (conf->phy_lowreset) {
writel(VAL0 | PHY_RST_POL | RESET_PHY , (void *)(mmio + CMD3));
write32((void *)(mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
} else {
writel(VAL0 | RESET_PHY, (void *)(mmio + CMD3));
write32((void *)(mmio + CMD3), VAL0 | RESET_PHY);
}
mdelay(15);
writel(RESET_PHY, (void *)(mmio + CMD3));
write32((void *)(mmio + CMD3), RESET_PHY);
printk_debug("Done\n");
}

54
src/southbridge/amd/cs5530/cs5530_vga.c
View File

@ -242,27 +242,27 @@ static void cs5530_set_clock_frequency(void *io_base, unsigned long pll_val)
unsigned long reg;
/* disable the PLL first, reset and power it down */
reg = readl(io_base+CS5530_DOT_CLK_CONFIG) & ~0x20;
reg = read32(io_base+CS5530_DOT_CLK_CONFIG) & ~0x20;
reg |= 0x80000100;
writel(reg, io_base+CS5530_DOT_CLK_CONFIG);
write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
/* write the new PLL setting */
reg |= (pll_val & ~0x80000920);
writel(reg, io_base+CS5530_DOT_CLK_CONFIG);
write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
mdelay(1); /* wait for control voltage to be 0V */
/* enable the PLL */
reg |= 0x00000800;
writel(reg, io_base+CS5530_DOT_CLK_CONFIG);
write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
/* clear reset */
reg &= ~0x80000000;
writel(reg, io_base+CS5530_DOT_CLK_CONFIG);
write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
/* clear bypass */
reg &= ~0x00000100;
writel(reg, io_base+CS5530_DOT_CLK_CONFIG);
write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
}
/**
@ -286,15 +286,15 @@ static void dc_setup_layout(void *gx_base, const struct video_mode *mode)
{
u32 base = 0x00000000;
writel(base, gx_base + DC_FB_ST_OFFSET);
write32(gx_base + DC_FB_ST_OFFSET, base);
base += (COLOUR_DEPTH>>3) * mode->visible_pixel * mode->visible_lines;
writel(base, gx_base + DC_CB_ST_OFFSET);
writel(base, gx_base + DC_CURS_ST_OFFSET);
writel(base, gx_base + DC_VID_ST_OFFSET);
writel(((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 2, gx_base + DC_LINE_DELTA);
writel(((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 3, gx_base + DC_BUF_SIZE);
write32(gx_base + DC_CB_ST_OFFSET, base);
write32(gx_base + DC_CURS_ST_OFFSET, base);
write32(gx_base + DC_VID_ST_OFFSET, base);
write32(gx_base + DC_LINE_DELTA, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 2);
write32(gx_base + DC_BUF_SIZE, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 3);
}
/**
@ -343,20 +343,20 @@ static void dc_setup_timing(void *gx_base, const struct video_mode *mode)
vtotal = vblankend;
/* row description */
writel((hactive - 1) | ((htotal - 1) << 16), gx_base + DC_H_TIMING_1);
write32(gx_base + DC_H_TIMING_1, (hactive - 1) | ((htotal - 1) << 16));
/* horizontal blank description */
writel((hblankstart - 1) | ((hblankend - 1) << 16), gx_base + DC_H_TIMING_2);
write32(gx_base + DC_H_TIMING_2, (hblankstart - 1) | ((hblankend - 1) << 16));
/* horizontal sync description */
writel((hsyncstart - 1) | ((hsyncend - 1) << 16), gx_base + DC_H_TIMING_3);
writel((hsyncstart - 1) | ((hsyncend - 1) << 16), gx_base + DC_FP_H_TIMING);
write32(gx_base + DC_H_TIMING_3, (hsyncstart - 1) | ((hsyncend - 1) << 16));
write32(gx_base + DC_FP_H_TIMING, (hsyncstart - 1) | ((hsyncend - 1) << 16));
/* line description */
writel((vactive - 1) | ((vtotal - 1) << 16), gx_base + DC_V_TIMING_1);
write32(gx_base + DC_V_TIMING_1, (vactive - 1) | ((vtotal - 1) << 16));
/* vertical blank description */
writel((vblankstart - 1) | ((vblankend - 1) << 16), gx_base + DC_V_TIMING_2);
write32(gx_base + DC_V_TIMING_2, (vblankstart - 1) | ((vblankend - 1) << 16));
/* vertical sync description */
writel((vsyncstart - 1) | ((vsyncend - 1) << 16), gx_base + DC_V_TIMING_3);
writel((vsyncstart - 2) | ((vsyncend - 2) << 16), gx_base + DC_FP_V_TIMING);
write32(gx_base + DC_V_TIMING_3, (vsyncstart - 1) | ((vsyncend - 1) << 16));
write32(gx_base + DC_FP_V_TIMING, (vsyncstart - 2) | ((vsyncend - 2) << 16));
}
/**
@ -369,14 +369,14 @@ static void dc_setup_timing(void *gx_base, const struct video_mode *mode)
*/
static void cs5530_activate_mode(void *gx_base, const struct video_mode *mode)
{
writel(0x00000080, gx_base + DC_GENERAL_CFG);
write32(gx_base + DC_GENERAL_CFG, 0x00000080);
mdelay(1);
dc_setup_layout(gx_base,mode);
dc_setup_timing(gx_base,mode);
writel(0x2000C581, gx_base + DC_GENERAL_CFG);
writel(0x0000002F, gx_base + DC_TIMING_CFG);
writel(0x00003004, gx_base + DC_OUTPUT_CFG);
write32(gx_base + DC_GENERAL_CFG, 0x2000C581);
write32(gx_base + DC_TIMING_CFG, 0x0000002F);
write32(gx_base + DC_OUTPUT_CFG, 0x00003004);
}
/**
@ -392,7 +392,7 @@ static void cs5530_activate_video(void *io_base, const struct video_mode *mode)
u32 val;
val = (u32)mode->sync_pol << 8;
writel(val | 0x0020002F, io_base + CS5530_DISPLAY_CONFIG);
write32(io_base + CS5530_DISPLAY_CONFIG, val | 0x0020002F);
}
#if CONFIG_SPLASH_GRAPHIC == 1
@ -465,7 +465,7 @@ static void cs5530_vga_init(device_t dev)
cs5530_set_clock_frequency(io_base, mode->pll_value);
writel(DC_UNLOCK_MAGIC, gx_base + DC_UNLOCK);
write32(gx_base + DC_UNLOCK, DC_UNLOCK_MAGIC);
show_boot_splash_16(mode->visible_pixel, mode->visible_lines,
mode->visible_pixel * (COLOUR_DEPTH>>3), (void*)(GX_BASE + 0x800000));
@ -473,7 +473,7 @@ static void cs5530_vga_init(device_t dev)
cs5530_activate_mode(gx_base, mode);
cs5530_activate_video(io_base, mode);
writel(0x00000000, gx_base + DC_UNLOCK);
write32(gx_base + DC_UNLOCK, 0x00000000);
}
static struct device_operations vga_ops = {

22
src/southbridge/amd/cs5536/cs5536.c
View File

@ -428,10 +428,10 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
/* Make HCCPARAMS writeable */
writel(readl(bar + IPREG04) | USB_HCCPW_SET, bar + IPREG04);
write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);
/* ; EECP=50h, IST=01h, ASPC=1 */
writel(0x00005012, bar + HCCPARAMS);
write32(bar + HCCPARAMS, 0x00005012);
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
@ -439,19 +439,19 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
if (dev) {
bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
writel(readl(bar + UOCMUX) & PUEN_SET, bar + UOCMUX);
write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET);
/* Host or Device? */
if (sb->enable_USBP4_device) {
writel(readl(bar + UOCMUX) | PMUX_DEVICE, bar + UOCMUX);
write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_DEVICE);
} else {
writel(readl(bar + UOCMUX) | PMUX_HOST, bar + UOCMUX);
write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_HOST);
}
/* Overcurrent configuration */
if (sb->enable_USBP4_overcurrent) {
writel(readl(bar + UOCCAP)
| sb->enable_USBP4_overcurrent, bar + UOCCAP);
write32(bar + UOCCAP, read32(bar + UOCCAP)
| sb->enable_USBP4_overcurrent);
}
}
@ -467,8 +467,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
if (dev) {
bar = (uint8_t *) pci_read_config32(dev,
PCI_BASE_ADDRESS_0);
writel(readl(bar + UDCDEVCTL) | UDC_SD_SET,
bar + UDCDEVCTL);
write32(bar + UDCDEVCTL,
read32(bar + UDCDEVCTL) | UDC_SD_SET);
}
@ -477,8 +477,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
if (dev) {
bar = (uint8_t *) pci_read_config32(dev,
PCI_BASE_ADDRESS_0);
writel(readl(bar + UOCCTL) | PADEN_SET, bar + UOCCTL);
writel(readl(bar + UOCCAP) | APU_SET, bar + UOCCAP);
write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET);
write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET);
}
}

18
src/southbridge/amd/sb600/sb600_hda.c
View File

@ -37,10 +37,10 @@ static int set_bits(u8 * port, u32 mask, u32 val)
/* Write (val & ~mask) to port */
val &= mask;
dword = readl(port);
dword = read32(port);
dword &= ~mask;
dword |= val;
writel(dword, port);
write32(port, dword);
/* Wait for readback of register to
* match what was just written to it
@ -49,7 +49,7 @@ static int set_bits(u8 * port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
dword = readl(port);
dword = read32(port);
dword &= mask;
} while ((dword != val) && --count);
@ -75,7 +75,7 @@ static u32 codec_detect(u8 * base)
mdelay(1);
/* Read in Codec location (BAR + 0xe)[3..0]*/
dword = readl(base + 0xe);
dword = read32(base + 0xe);
dword &= 0x0F;
if (!dword)
goto no_codec;
@ -180,7 +180,7 @@ static int wait_for_ready(u8 *base)
int timeout = 50;
while(timeout--) {
u32 dword=readl(base + HDA_ICII_REG);
u32 dword=read32(base + HDA_ICII_REG);
if (!(dword & HDA_ICII_BUSY))
return 0;
udelay(1);
@ -202,7 +202,7 @@ static int wait_for_valid(u8 *base)
int timeout = 50;
while(timeout--) {
u32 dword = readl(base + HDA_ICII_REG);
u32 dword = read32(base + HDA_ICII_REG);
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@ -224,12 +224,12 @@ static void codec_init(u8 * base, int addr)
return;
dword = (addr << 28) | 0x000f0000;
writel(dword, base + 0x60);
write32(base + 0x60, dword);
if (wait_for_valid(base) == -1)
return;
dword = readl(base + 0x64);
dword = read32(base + 0x64);
/* 2 */
printk_debug("codec viddid: %08x\n", dword);
@ -246,7 +246,7 @@ static void codec_init(u8 * base, int addr)
if (wait_for_ready(base) == -1)
return;
writel(verb[i], base + 0x60);
write32(base + 0x60, verb[i]);
if (wait_for_valid(base) == -1)
return;

24
src/southbridge/amd/sb600/sb600_sata.c
View File

@ -172,7 +172,7 @@ static void sata_init(struct device *dev)
/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
for (i = 0; i < 4; i++) {
byte = readb(sata_bar5 + 0x128 + 0x80 * i);
byte = read8(sata_bar5 + 0x128 + 0x80 * i);
printk_spew("SATA port %i status = %x\n", i, byte);
byte &= 0xF;
@ -182,24 +182,24 @@ static void sata_init(struct device *dev)
printk_spew("SATA device detected but not talking. Trying lower speed.\n");
/* Read in Port-N Serial ATA Control Register */
byte = readb(sata_bar5 + 0x12C + 0x80 * i);
byte = read8(sata_bar5 + 0x12C + 0x80 * i);
/* Set Reset Bit and 1.5g bit */
byte |= 0x11;
writeb(byte, (sata_bar5 + 0x12C + 0x80 * i));
write8((sata_bar5 + 0x12C + 0x80 * i), byte);
/* Wait 1ms */
mdelay(1);
/* Clear Reset Bit */
byte &= ~0x01;
writeb(byte, (sata_bar5 + 0x12C + 0x80 * i));
write8((sata_bar5 + 0x12C + 0x80 * i), byte);
/* Wait 1ms */
mdelay(1);
/* Reread status */
byte = readb(sata_bar5 + 0x128 + 0x80 * i);
byte = read8(sata_bar5 + 0x128 + 0x80 * i);
printk_spew("SATA port %i status = %x\n", i, byte);
byte &= 0xF;
}
@ -223,15 +223,15 @@ static void sata_init(struct device *dev)
/* Below is CIM InitSataLateFar */
/* Enable interrupts from the HBA */
byte = readb(sata_bar5 + 0x4);
byte = read8(sata_bar5 + 0x4);
byte |= 1 << 1;
writeb(byte, (sata_bar5 + 0x4));
write8((sata_bar5 + 0x4), byte);
/* Clear error status */
writel(0xFFFFFFFF, (sata_bar5 + 0x130));
writel(0xFFFFFFFF, (sata_bar5 + 0x1b0));
writel(0xFFFFFFFF, (sata_bar5 + 0x230));
writel(0xFFFFFFFF, (sata_bar5 + 0x2b0));
write32((sata_bar5 + 0x130), 0xFFFFFFFF);
write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
write32((sata_bar5 + 0x230), 0xFFFFFFFF);
write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
@ -241,7 +241,7 @@ static void sata_init(struct device *dev)
/* byte = pm_ioread(0x29); */
/* word |= byte<<8; */
/* printk_debug("AcpiGpe0Blk addr = %x\n", word); */
/* writel(0x80000000 , word); */
/* write32(word, 0x80000000); */
}
static struct pci_operations lops_pci = {

8
src/southbridge/amd/sb600/sb600_usb.c
View File

@ -98,16 +98,16 @@ static void usb_init2(struct device *dev)
/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */
dword = 0x00020F00;
writel(dword, usb2_bar0 + 0xC0);
write32(usb2_bar0 + 0xC0, dword);
/* RPR5.5 Sets In/OUT FIFO threshold for best performance */
dword = 0x00200040;
writel(dword, usb2_bar0 + 0xA4);
write32(usb2_bar0 + 0xA4, dword);
/* RPR5.9 Disable the EHCI Dynamic Power Saving feature */
word = readl(usb2_bar0 + 0xBC);
word = read16(usb2_bar0 + 0xBC);
word &= ~(1 << 12);
writew(word, usb2_bar0 + 0xBC);
write16(usb2_bar0 + 0xBC, word);
/* RPR5.10 Disable EHCI MSI support */
byte = pci_read_config8(dev, 0x50);

10
src/southbridge/broadcom/bcm5785/bcm5785_sata.c
View File

@ -52,13 +52,13 @@ static void sata_init(struct device *dev)
printk_debug("init PHY...\n");
for(i=0; i<4; i++) {
mmio = base + 0x100 * i;
byte = readb(mmio + 0x40);
byte = read8(mmio + 0x40);
printk_debug("port %d PHY status = %02x\r\n", i, byte);
if(byte & 0x4) {// bit 2 is set
byte = readb(mmio+0x48);
writeb(byte | 1, mmio + 0x48);
writeb(byte & (~1), mmio + 0x48);
byte = readb(mmio + 0x40);
byte = read8(mmio+0x48);
write8(mmio + 0x48, byte | 1);
write8(mmio + 0x48, byte & (~1));
byte = read8(mmio + 0x40);
printk_debug("after reset port %d PHY status = %02x\r\n", i, byte);
}
}

22
src/southbridge/intel/i82801gx/i82801gx_azalia.c
View File

@ -40,10 +40,10 @@ static int set_bits(u8 * port, u32 mask, u32 val)
/* Write (val & mask) to port */
val &= mask;
reg32 = readl(port);
reg32 = read32(port);
reg32 &= ~mask;
reg32 |= val;
writel(reg32, port);
write32(port, reg32);
/* Wait for readback of register to
* match what was just written to it
@ -52,7 +52,7 @@ static int set_bits(u8 * port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
reg32 = readl(port);
reg32 = read32(port);
reg32 &= mask;
} while ((reg32 != val) && --count);
@ -75,7 +75,7 @@ static int codec_detect(u8 * base)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/
reg32 = readl(base + 0xe);
reg32 = read32(base + 0xe);
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
@ -124,7 +124,7 @@ static int wait_for_ready(u8 *base)
int timeout = 50;
while(timeout--) {
u32 reg32 = readl(base + HDA_ICII_REG);
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@ -144,16 +144,16 @@ static int wait_for_valid(u8 *base)
u32 reg32;
/* Send the verb to the codec */
reg32 = readl(base + 0x68);
reg32 = read32(base + 0x68);
reg32 |= (1 << 0) | (1 << 1);
writel(reg32, base + 0x68);
write32(base + 0x68, reg32);
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
reg32 = readl(base + HDA_ICII_REG);
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@ -177,12 +177,12 @@ static void codec_init(struct device *dev, u8 * base, int addr)
return;
reg32 = (addr << 28) | 0x000f0000;
writel(reg32, base + 0x60);
write32(base + 0x60, reg32);
if (wait_for_valid(base) == -1)
return;
reg32 = readl(base + 0x64);
reg32 = read32(base + 0x64);
/* 2 */
printk_debug("Azalia: codec viddid: %08x\n", reg32);
@ -199,7 +199,7 @@ static void codec_init(struct device *dev, u8 * base, int addr)
if (wait_for_ready(base) == -1)
return;
writel(verb[i], base + 0x60);
write32(base + 0x60, verb[i]);
if (wait_for_valid(base) == -1)
return;

5
src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
View File

@ -31,10 +31,9 @@ void set_debug_port(unsigned port)
u32 dbgctl;
printk_debug("Enabling OWNER_CNT\n");
dbgctl = readl(EHCI_BAR + EHCI_DEBUG_OFFSET);
dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30);
writel(dbgctl, EHCI_BAR + EHCI_DEBUG_OFFSET);
write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl);
}
static void i82801gx_enable_usbdebug_direct(unsigned port)

4
src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
View File

@ -53,8 +53,8 @@ static void usb_ehci_init(struct device *dev)
/* Clear any pending port changes */
res = find_resource(dev, 0x10);
base = res->base;
reg32 = readl((u8 *)base + 0x24) | (1 << 2);
writel(reg32, (u8 *)base + 0x24);
reg32 = read32((u8 *)base + 0x24) | (1 << 2);
write32((u8 *)base + 0x24, reg32);
/* workaround */
reg8 = pci_read_config8(dev, 0x84);

10
src/southbridge/nvidia/ck804/ck804_nic.c
View File

@ -27,7 +27,7 @@ static void nic_init(struct device *dev)
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
writel(PHY_RGMII, base + NvRegPhyInterface);
write32(base + NvRegPhyInterface, PHY_RGMII);
old = dword = pci_read_config32(dev, 0x30);
dword &= ~(0xf);
@ -76,15 +76,15 @@ static void nic_init(struct device *dev)
if (!eeprom_valid) {
unsigned long mac_pos;
mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
mac_l = readl((uint8_t*)mac_pos) + nic_index;
mac_h = readl((uint8_t*)mac_pos + 4);
mac_l = read32((uint8_t*)mac_pos) + nic_index;
mac_h = read32((uint8_t*)mac_pos + 4);
}
#if 1
/* Set that into NIC MMIO. */
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
writel(mac_l, base + NvRegMacAddrA);
writel(mac_h, base + NvRegMacAddrB);
write32(base + NvRegMacAddrA, mac_l);
write32(base + NvRegMacAddrB, mac_h);
#else
/* Set that into NIC. */
pci_write_config32(dev, 0xa8, mac_l);

26
src/southbridge/nvidia/mcp55/mcp55_aza.c
View File

@ -36,14 +36,14 @@ static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
int count;
val &= mask;
dword = readl(port);
dword = read32(port);
dword &= ~mask;
dword |= val;
writel(dword, port);
write32(port, dword);
count = 50;
do {
dword = readl(port);
dword = read32(port);
dword &= mask;
udelay(100);
} while ((dword != val) && --count);
@ -63,9 +63,9 @@ static int codec_detect(uint8_t *base)
set_bits(base + 0x08, 1, 1);
/* 2 */
dword = readl(base + 0x0e);
dword = read32(base + 0x0e);
dword |= 7;
writel(dword, base + 0x0e);
write32(base + 0x0e, dword);
/* 3 */
set_bits(base + 0x08, 1, 0);
@ -74,7 +74,7 @@ static int codec_detect(uint8_t *base)
set_bits(base + 0x08, 1, 1);
/* 5 */
dword = readl(base + 0xe);
dword = read32(base + 0xe);
dword &= 7;
/* 6 */
@ -173,17 +173,17 @@ static void codec_init(uint8_t *base, int addr)
/* 1 */
do {
dword = readl(base + 0x68);
dword = read32(base + 0x68);
} while (dword & 1);
dword = (addr<<28) | 0x000f0000;
writel(dword, base + 0x60);
write32(base + 0x60, dword);
do {
dword = readl(base + 0x68);
dword = read32(base + 0x68);
} while ((dword & 3)!=2);
dword = readl(base + 0x64);
dword = read32(base + 0x64);
/* 2 */
printk_debug("codec viddid: %08x\n", dword);
@ -198,13 +198,13 @@ static void codec_init(uint8_t *base, int addr)
/* 3 */
for(i=0; i<verb_size; i++) {
do {
dword = readl(base + 0x68);
dword = read32(base + 0x68);
} while (dword & 1);
writel(verb[i], base + 0x60);
write32(base + 0x60, verb[i]);
do {
dword = readl(base + 0x68);
dword = read32(base + 0x68);
} while ((dword & 3) != 2);
}
printk_debug("verb loaded!\n");

28
src/southbridge/nvidia/mcp55/mcp55_nic.c
View File

@ -35,22 +35,22 @@ static int phy_read(uint8_t *base, unsigned phy_addr, unsigned phy_reg)
{
uint32_t dword;
unsigned loop = 0x100;
writel(0x8000, base+0x190); //Clear MDIO lock bit
write32(base+0x190, 0x8000); //Clear MDIO lock bit
mdelay(1);
dword = readl(base+0x190);
dword = read32(base+0x190);
if(dword & (1<<15)) return -1;
writel(1, base+0x180);
writel((phy_addr<<5) | (phy_reg),base + 0x190);
write32(base+0x180, 1);
write32(base + 0x190, (phy_addr<<5) | (phy_reg));
do{
dword = readl(base + 0x190);
dword = read32(base + 0x190);
if(--loop==0) return -4;
} while ((dword & (1<<15)) );
dword = readl(base + 0x180);
dword = read32(base + 0x180);
if(dword & 1) return -3;
dword = readl(base + 0x194);
dword = read32(base + 0x194);
return dword;
@ -62,9 +62,9 @@ static void phy_detect(uint8_t *base)
int i;
int val;
unsigned id;
dword = readl(base+0x188);
dword = read32(base+0x188);
dword &= ~(1<<20);
writel(dword, base+0x188);
write32(base+0x188, dword);
phy_read(base, 0, 1);
@ -116,7 +116,7 @@ static void nic_init(struct device *dev)
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
writel(PHY_RGMII, base + NvRegPhyInterface);
write32(base + NvRegPhyInterface, PHY_RGMII);
conf = dev->chip_info;
@ -157,16 +157,16 @@ static void nic_init(struct device *dev)
if(!eeprom_valid) {
unsigned long mac_pos;
mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
mac_l = readl(mac_pos) + nic_index; // overflow?
mac_h = readl(mac_pos + 4);
mac_l = read32(mac_pos) + nic_index; // overflow?
mac_h = read32(mac_pos + 4);
}
#if 1
// set that into NIC MMIO
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
writel(mac_l, base + NvRegMacAddrA);
writel(mac_h, base + NvRegMacAddrB);
write32(base + NvRegMacAddrA, mac_l);
write32(base + NvRegMacAddrB, mac_h);
#else
// set that into NIC
pci_write_config32(dev, 0xa8, mac_l);

32
src/southbridge/sis/sis966/sis966_aza.c
View File

@ -48,14 +48,14 @@ static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
int count;
val &= mask;
dword = readl(port);
dword = read32(port);
dword &= ~mask;
dword |= val;
writel(dword, port);
write32(port, dword);
count = 50;
do {
dword = readl(port);
dword = read32(port);
dword &= mask;
udelay(100);
} while ((dword != val) && --count);
@ -73,23 +73,23 @@ static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
uint32_t dword;
dword = readl(base + 0x68);
dword = read32(base + 0x68);
dword=dword|(unsigned long)0x0002;
writel(dword,base + 0x68);
write32(base + 0x68, dword);
do {
dword = readl(base + 0x68);
dword = read32(base + 0x68);
} while ((dword & 1)!=0);
writel(verb, base + 0x60);
write32(base + 0x60, verb);
udelay(500);
dword = readl(base + 0x68);
dword = read32(base + 0x68);
dword =(dword |0x1);
writel(dword, base + 0x68);
write32(base + 0x68, dword);
do {
udelay(100);
dword = readl(base + 0x68);
dword = read32(base + 0x68);
} while ((dword & 3) != 2);
dword = readl(base + 0x64);
dword = read32(base + 0x64);
return dword;
}
@ -106,7 +106,7 @@ static int codec_detect(uint8_t *base)
set_bits(base + 0x08, 1, 1);
do{
dword = readl(base + 0x08)&0x1;
dword = read32(base + 0x08)&0x1;
if(idx++>1000) { printk_debug("controller reset fail !!! \n"); break;}
} while (dword !=1);
@ -206,17 +206,17 @@ static void codec_init(uint8_t *base, int addr)
/* 1 */
do {
dword = readl(base + 0x68);
dword = read32(base + 0x68);
} while (dword & 1);
dword = (addr<<28) | 0x000f0000;
writel(dword, base + 0x60);
write32(base + 0x60, dword);
do {
dword = readl(base + 0x68);
dword = read32(base + 0x68);
} while ((dword & 3)!=2);
dword = readl(base + 0x64);
dword = read32(base + 0x64);
/* 2 */
printk_debug("codec viddid: %08x\n", dword);

18
src/southbridge/sis/sis966/sis966_nic.c
View File

@ -144,13 +144,13 @@ static unsigned long ReadEEprom( struct device *dev, uint32_t base, uint32_t
ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7
writel( ulValue,base+0x3c);
write32(base+0x3c, ulValue);
mdelay(10);
for(i=0 ; i <= LoopNum; i++)
{
ulValue=readl(base+0x3c);
ulValue=read32(base+0x3c);
if(!(ulValue & 0x0080)) //BIT_7
break;
@ -162,7 +162,7 @@ static unsigned long ReadEEprom( struct device *dev, uint32_t base, uint32_t
if(i==LoopNum) data=0x10000;
else{
ulValue=readl(base+0x3c);
ulValue=read32(base+0x3c);
data = ((ulValue & 0xffff0000) >> 16);
}
@ -183,14 +183,14 @@ static int phy_read(uint32_t base, unsigned phy_addr, unsigned phy_reg)
SMI_REQUEST);
// SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
writel( Read_Cmd,base+0x44);
write32(base+0x44, Read_Cmd);
// Polling SMI_REQ bit to be deasserted indicated read command completed
do
{
// Wait 20 usec before checking status
mdelay(20);
ulValue = readl(base+0x44);
ulValue = read32(base+0x44);
} while((ulValue & SMI_REQUEST) != 0);
//printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
usData=(ulValue>>16);
@ -282,7 +282,7 @@ static void nic_init(struct device *dev)
return;
}
ulValue=readl(base + 0x38L); // check EEPROM existing
ulValue=read32(base + 0x38L); // check EEPROM existing
if((ulValue & 0x0002))
{
@ -303,9 +303,9 @@ static void nic_init(struct device *dev)
}else{
// read MAC address from firmware
printk_debug("EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
MacAddr[0]=readw(0xffffffc0); // mac address store at here
MacAddr[1]=readw(0xffffffc2);
MacAddr[2]=readw(0xffffffc4);
MacAddr[0]=read16(0xffffffc0); // mac address store at here
MacAddr[1]=read16(0xffffffc2);
MacAddr[2]=read16(0xffffffc4);
}
set_apc(dev);

2
src/southbridge/sis/sis966/sis966_usb2.c
View File

@ -96,7 +96,7 @@ static void usb2_init(struct device *dev)
base =(uint8_t *) res->base;
printk_debug("base = %08x\n", base);
writel(0x2,base+0x20);
write32(base+0x20, 0x2);
//-----------------------------------------------------------
#if DEBUG_USB2