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mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads 

This change uses cnl_configure_pads to configure GPIOs in ramstage so
that cannonlake SoC code can re-configure the GPIOs after FSP-S is
run. This is just adding a workaround until FSP-S is fixed.

BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.

Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2019-02-05 14:03:44 -08:00 committed by Patrick Georgi
parent 86d2afb86b
commit a08765d287
2 changed files with 4 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/hatch/ramstage.c
View File

@ -16,6 +16,7 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <ec/ec.h> #include <ec/ec.h>
#include <soc/gpio.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include <variant/gpio.h> #include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
@ -26,7 +27,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
size_t num_gpios; size_t num_gpios;
gpio_table = variant_gpio_table(&num_gpios); gpio_table = variant_gpio_table(&num_gpios);
gpio_configure_pads(gpio_table, num_gpios); cnl_configure_pads(gpio_table, num_gpios);
} }
static void mainboard_enable(struct device *dev) static void mainboard_enable(struct device *dev)

14
src/mainboard/google/sarien/ramstage.c
View File

@ -14,6 +14,7 @@
*/ */
#include <arch/acpi.h> #include <arch/acpi.h>
#include <soc/gpio.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include <variant/gpio.h> #include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
@ -24,22 +25,11 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
size_t num_gpios; size_t num_gpios;
gpio_table = variant_gpio_table(&num_gpios); gpio_table = variant_gpio_table(&num_gpios);
gpio_configure_pads(gpio_table, num_gpios); cnl_configure_pads(gpio_table, num_gpios);
}
/* Workaround FSP issue by reprogramming GPIOs after FSP-S */
static void mainboard_init(struct device *dev)
{
const struct pad_config *gpio_table;
size_t num_gpios;
gpio_table = variant_gpio_table(&num_gpios);
gpio_configure_pads(gpio_table, num_gpios);
} }
static void mainboard_enable(struct device *dev) static void mainboard_enable(struct device *dev)
{ {
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
} }