sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x

The northbridge code to set up DMI is not correct and the CIR bits
relate to that.

This fixes a regression caused by 2437fe9 'sb/intel/i82801gx: Move CIR
init to a common place', where payloads hang on southbridge IO.

Change-Id: Iabb54d9954d442a1a7b48a6c6e76faa8079a4c71
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36809
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/southbridge/intel/i82801gx/early_init.c

@@ -112,6 +112,9 @@ void i82801gx_early_init(void)
 	RCBA8(OIC) = 0x03;
 	RCBA8(OIC);
 
+	/* A lot of CIR bits relate DMI setup which is likely not correctly
+	   done for x4x. The issue is also present on ICH10. */
+	if (!CONFIG(NORTHBRIDGE_INTEL_X4X))
 		ich7_setup_cir();
 }
 #endif