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amd/mct: Add default values to highest_rank_count for DDR2 

The values of highest_rank_count were undefined on DDR2 systems.
Explcitly define these values on DDR2 platforms.

Found-by: Coverity Scan #1347338
Change-Id: Iad7bb00db97b2816fcc44fb5941bd14373451da2
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18078
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2017-01-09 17:47:37 -06:00
parent 9d490daf8d
commit a19d44d276
1 changed files with 2 additions and 3 deletions
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5
src/northbridge/amd/amdmct/wrappers/mcti_d.c
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@ -344,6 +344,7 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
uint8_t ch1_voltage = 0;
uint8_t ch2_voltage = 0;
uint8_t highest_rank_count[2];
uint8_t dimm;
int i;
for (i = 0; i < 15; i = i + 2) {
if (pDCTstat->DIMMValid & (1 << i))
@ -363,14 +364,13 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
}
#if IS_ENABLED(CONFIG_DIMM_DDR3)
uint8_t dimm;
for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) {
if (pDCTstat->DIMMValid & (1 << i))
ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i];
if (pDCTstat->DIMMValid & (1 << (i + 1)))
ch2_voltage |= pDCTstat->DimmConfiguredVoltage[i + 1];
}
#endif
for (i = 0; i < 2; i++) {
highest_rank_count[i] = 0x0;
@ -379,7 +379,6 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
highest_rank_count[i] = pDCTstat->DimmRanks[dimm];
}
}
#endif
/* Set limits if needed */
pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), max(highest_rank_count[0], highest_rank_count[1]), (ch1_registered || ch2_registered), (ch1_voltage | ch2_voltage), pDCTstat->PresetmaxFreq);