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mb/google/mancomb: Fix TPM setting in devicetree 

Fix I2C3 setting for TPM in devicetree.

BUG=b:187341277
TEST=Build and boot into OS

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I728da76cee0c92c29df4c6ee8bfb4cd07a6366c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Ivy Jian 2021-05-07 10:50:49 +08:00 committed by Martin Roth
parent a8779941dc
commit a204cdf75b
1 changed files with 9 additions and 8 deletions
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17
src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
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@ -121,16 +121,17 @@ chip soc/amd/cezanne
device pnp 0c09.0 on end device pnp 0c09.0 on end
end end
end end
device ref i2c_3 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "desc" = ""Cr50 TPM""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)"
device i2c 50 on end
end
end
end # domain end # domain
device ref i2c_3 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "desc" = ""Cr50 TPM""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)"
device i2c 50 on end
end
end
device ref uart_0 on end # UART0 device ref uart_0 on end # UART0
end # chip soc/amd/cezanne end # chip soc/amd/cezanne