soc/mediatek: Add an overridable function for WDT clear status

mtk_wdt_clr_status is different for MT8186 and MT8195,
so we move this function to soc folder.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/common/Kconfig

@@ -29,11 +29,6 @@ config MEMORY_TEST
 	  This option enables memory basic compare test to verify the DRAM read
 	  or write is as expected.
 
-config CLEAR_WDT_MODE_REG
-	bool
-	help
-	  Enable this option to clear WTD mode register explicitly.
-
 config DPM_FOUR_CHANNEL
 	bool
 	default n

src/soc/mediatek/common/include/soc/wdt.h

@@ -21,7 +21,6 @@ struct mtk_wdt_regs {
 /* WDT_MODE */
 enum {
 	MTK_WDT_MODE_KEY	= 0x22000000,
-	MTK_WDT_CLR_STATUS	= 0x230001FF,
 	MTK_WDT_MODE_DUAL_MODE	= 1 << 6,
 	MTK_WDT_MODE_IRQ	= 1 << 3,
 	MTK_WDT_MODE_EXTEN	= 1 << 2,
@@ -40,5 +39,6 @@ enum {
 static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE;
 
 int mtk_wdt_init(void);
+void mtk_wdt_clr_status(uint32_t wdt_sta);
 
 #endif /* SOC_MEDIATEK_COMMON_WDT_H */

src/soc/mediatek/common/wdt.c

@@ -5,6 +5,8 @@
 #include <soc/wdt.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+__weak void mtk_wdt_clr_status(uint32_t wdt_sta) { /* do nothing */ }
+
 int mtk_wdt_init(void)
 {
 	uint32_t wdt_sta;
@@ -12,8 +14,7 @@ int mtk_wdt_init(void)
 	/* Writing mode register will clear status register */
 	wdt_sta = read32(&mtk_wdt->wdt_status);
 
-	if (CONFIG(CLEAR_WDT_MODE_REG))
+	mtk_wdt_clr_status(wdt_sta);
-		write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS);
 
 	printk(BIOS_INFO, "WDT: Last reset was ");
 	if (wdt_sta & MTK_WDT_STA_HW_RST) {

src/soc/mediatek/mt8195/Kconfig

@@ -9,7 +9,6 @@ config SOC_MEDIATEK_MT8195
 	select CACHE_MRC_SETTINGS
 	select HAVE_UART_SPECIAL
 	select SOC_MEDIATEK_COMMON
-	select CLEAR_WDT_MODE_REG
 	select DPM_FOUR_CHANNEL
 
 if SOC_MEDIATEK_MT8195

src/soc/mediatek/mt8195/Makefile.inc

@@ -11,7 +11,7 @@ bootblock-y += ../common/pll.c pll.c
 bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 bootblock-y += ../common/timer.c timer.c
 bootblock-y += ../common/uart.c
-bootblock-y += ../common/wdt.c
+bootblock-y += ../common/wdt.c wdt.c
 
 verstage-y += ../common/auxadc.c
 verstage-y += ../common/flash_controller.c
@@ -20,7 +20,7 @@ verstage-y += ../common/i2c.c i2c.c
 verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 verstage-y += ../common/timer.c timer.c
 verstage-y += ../common/uart.c
-verstage-y += ../common/wdt.c
+verstage-y += ../common/wdt.c wdt.c
 
 ramstage-y += apusys.c
 romstage-y += ../common/auxadc.c
@@ -40,7 +40,7 @@ romstage-y += scp.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/timer.c timer.c
 romstage-y += ../common/uart.c
-romstage-y += ../common/wdt.c
+romstage-y += ../common/wdt.c wdt.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
 romstage-y += ../common/pmif_spmi.c pmif_spmi.c
@@ -79,7 +79,7 @@ ramstage-y += ../common/timer.c timer.c
 ramstage-y += ../common/uart.c
 ramstage-y += ../common/ufs.c
 ramstage-y += ../common/usb.c usb.c
-ramstage-y += ../common/wdt.c
+ramstage-y += ../common/wdt.c wdt.c
 
 BL31_MAKEARGS += PLAT=mt8195
 

src/soc/mediatek/mt8195/wdt.c

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/wdt.h>
+
+#define MTK_WDT_CLR_STATUS 0x230001FF
+
+void mtk_wdt_clr_status(uint32_t wdt_sta)
+{
+	write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS);
+}