soc/mediatek: Add an overridable function for WDT clear status
mtk_wdt_clr_status is different for MT8186 and MT8195, so we move this function to soc folder. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -29,11 +29,6 @@ config MEMORY_TEST
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This option enables memory basic compare test to verify the DRAM read
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This option enables memory basic compare test to verify the DRAM read
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or write is as expected.
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or write is as expected.
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config CLEAR_WDT_MODE_REG
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bool
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help
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Enable this option to clear WTD mode register explicitly.
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config DPM_FOUR_CHANNEL
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config DPM_FOUR_CHANNEL
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bool
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bool
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default n
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default n
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@ -21,7 +21,6 @@ struct mtk_wdt_regs {
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/* WDT_MODE */
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/* WDT_MODE */
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enum {
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enum {
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MTK_WDT_MODE_KEY = 0x22000000,
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MTK_WDT_MODE_KEY = 0x22000000,
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MTK_WDT_CLR_STATUS = 0x230001FF,
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MTK_WDT_MODE_DUAL_MODE = 1 << 6,
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MTK_WDT_MODE_DUAL_MODE = 1 << 6,
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MTK_WDT_MODE_IRQ = 1 << 3,
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MTK_WDT_MODE_IRQ = 1 << 3,
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MTK_WDT_MODE_EXTEN = 1 << 2,
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MTK_WDT_MODE_EXTEN = 1 << 2,
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@ -40,5 +39,6 @@ enum {
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static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE;
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static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE;
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int mtk_wdt_init(void);
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int mtk_wdt_init(void);
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void mtk_wdt_clr_status(uint32_t wdt_sta);
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#endif /* SOC_MEDIATEK_COMMON_WDT_H */
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#endif /* SOC_MEDIATEK_COMMON_WDT_H */
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@ -5,6 +5,8 @@
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#include <soc/wdt.h>
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#include <soc/wdt.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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__weak void mtk_wdt_clr_status(uint32_t wdt_sta) { /* do nothing */ }
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int mtk_wdt_init(void)
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int mtk_wdt_init(void)
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{
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{
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uint32_t wdt_sta;
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uint32_t wdt_sta;
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@ -12,8 +14,7 @@ int mtk_wdt_init(void)
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/* Writing mode register will clear status register */
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/* Writing mode register will clear status register */
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wdt_sta = read32(&mtk_wdt->wdt_status);
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wdt_sta = read32(&mtk_wdt->wdt_status);
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if (CONFIG(CLEAR_WDT_MODE_REG))
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mtk_wdt_clr_status(wdt_sta);
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write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS);
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printk(BIOS_INFO, "WDT: Last reset was ");
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printk(BIOS_INFO, "WDT: Last reset was ");
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if (wdt_sta & MTK_WDT_STA_HW_RST) {
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if (wdt_sta & MTK_WDT_STA_HW_RST) {
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@ -9,7 +9,6 @@ config SOC_MEDIATEK_MT8195
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select CACHE_MRC_SETTINGS
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select CACHE_MRC_SETTINGS
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select HAVE_UART_SPECIAL
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select HAVE_UART_SPECIAL
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select SOC_MEDIATEK_COMMON
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select SOC_MEDIATEK_COMMON
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select CLEAR_WDT_MODE_REG
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select DPM_FOUR_CHANNEL
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select DPM_FOUR_CHANNEL
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if SOC_MEDIATEK_MT8195
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if SOC_MEDIATEK_MT8195
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@ -11,7 +11,7 @@ bootblock-y += ../common/pll.c pll.c
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bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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bootblock-y += ../common/timer.c timer.c
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bootblock-y += ../common/timer.c timer.c
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bootblock-y += ../common/uart.c
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bootblock-y += ../common/uart.c
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bootblock-y += ../common/wdt.c
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bootblock-y += ../common/wdt.c wdt.c
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verstage-y += ../common/auxadc.c
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verstage-y += ../common/auxadc.c
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verstage-y += ../common/flash_controller.c
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verstage-y += ../common/flash_controller.c
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@ -20,7 +20,7 @@ verstage-y += ../common/i2c.c i2c.c
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verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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verstage-y += ../common/timer.c timer.c
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verstage-y += ../common/timer.c timer.c
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verstage-y += ../common/uart.c
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verstage-y += ../common/uart.c
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verstage-y += ../common/wdt.c
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verstage-y += ../common/wdt.c wdt.c
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ramstage-y += apusys.c
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ramstage-y += apusys.c
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romstage-y += ../common/auxadc.c
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romstage-y += ../common/auxadc.c
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@ -40,7 +40,7 @@ romstage-y += scp.c
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romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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romstage-y += ../common/timer.c timer.c
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romstage-y += ../common/timer.c timer.c
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romstage-y += ../common/uart.c
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romstage-y += ../common/uart.c
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romstage-y += ../common/wdt.c
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romstage-y += ../common/wdt.c wdt.c
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romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c
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romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c
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romstage-y += ../common/pmif_spi.c pmif_spi.c
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romstage-y += ../common/pmif_spi.c pmif_spi.c
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romstage-y += ../common/pmif_spmi.c pmif_spmi.c
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romstage-y += ../common/pmif_spmi.c pmif_spmi.c
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@ -79,7 +79,7 @@ ramstage-y += ../common/timer.c timer.c
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ramstage-y += ../common/uart.c
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ramstage-y += ../common/uart.c
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ramstage-y += ../common/ufs.c
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ramstage-y += ../common/ufs.c
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ramstage-y += ../common/usb.c usb.c
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ramstage-y += ../common/usb.c usb.c
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ramstage-y += ../common/wdt.c
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ramstage-y += ../common/wdt.c wdt.c
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BL31_MAKEARGS += PLAT=mt8195
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BL31_MAKEARGS += PLAT=mt8195
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <soc/addressmap.h>
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#include <soc/wdt.h>
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#define MTK_WDT_CLR_STATUS 0x230001FF
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void mtk_wdt_clr_status(uint32_t wdt_sta)
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{
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write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS);
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}
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