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soc/amd/picasso: Use gpp_clk_setup_common function 

In follow up to CB:80285 use gpp_clk_setup_common for picasso as well.

Change-Id: I68d498d08d5975037086c84ff2f7fdb265ee84d9
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80414
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Varshit Pandya 2024-02-09 18:34:15 +05:30 committed by Felix Held
parent ef513773ab
commit a2acdce8d1
3 changed files with 2 additions and 53 deletions
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1
src/soc/amd/picasso/Kconfig
View File

@ -39,6 +39,7 @@ config SOC_AMD_PICASSO
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
select SOC_AMD_COMMON_BLOCK_EMMC
select SOC_AMD_COMMON_BLOCK_EMMC_SKIP_POWEROFF
select SOC_AMD_COMMON_BLOCK_GPP_CLK
select SOC_AMD_COMMON_BLOCK_GRAPHICS
select SOC_AMD_COMMON_BLOCK_HAS_ESPI
select SOC_AMD_COMMON_BLOCK_HDA

39
src/soc/amd/picasso/fch.c
View File

@ -176,44 +176,7 @@ static void al2ahb_clock_gate(void)
static void gpp_clk_setup(void)
{
struct soc_amd_picasso_config *cfg = config_of_soc();
/* look-up table to be able to iterate over the PCIe clock output settings */
const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
GPP_CLK0_REQ_SHIFT,
GPP_CLK1_REQ_SHIFT,
GPP_CLK2_REQ_SHIFT,
GPP_CLK3_REQ_SHIFT,
GPP_CLK4_REQ_SHIFT,
GPP_CLK5_REQ_SHIFT,
GPP_CLK6_REQ_SHIFT,
};
uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
ARRAY_SIZE(cfg->gpp_clk_config));
for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
/*
* The remapping of values is done so that the default of the enum used for the
* devicetree settings is the clock being enabled, so that a missing devicetree
* configuration for this will result in an always active clock and not an
* inactive PCIe clock output.
*/
switch (cfg->gpp_clk_config[i]) {
case GPP_CLK_REQ:
gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
break;
case GPP_CLK_OFF:
gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]);
break;
case GPP_CLK_ON:
default:
gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]);
}
}
misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl);
gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config));
}
void fch_init(void *chip_info)

15
src/soc/amd/picasso/include/soc/southbridge.h
View File

@ -72,21 +72,6 @@
#define GPE0_LIMIT 32
#define TOTAL_BITS(a) (8 * sizeof(a))
/* FCH MISC Registers 0xfed80e00 */
#define GPP_CLK_CNTRL 0x00
#define GPP_CLK0_REQ_SHIFT 0
#define GPP_CLK1_REQ_SHIFT 2
#define GPP_CLK4_REQ_SHIFT 4
#define GPP_CLK2_REQ_SHIFT 6
#define GPP_CLK3_REQ_SHIFT 8
#define GPP_CLK5_REQ_SHIFT 10
#define GPP_CLK6_REQ_SHIFT 12
#define GPP_CLK_OUTPUT_COUNT 7
#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))
#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift))
#define MISC_CGPLL_CONFIG1 0x08
#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)
#define MISC_CLK_CNTL1 0x40