mediatek/mt8183: Add efuse calibration in auxadc

The values from auxadc may be incorrect if not calibrated by efuse.
Without calibration, the value error range is about +/-50mv,
and after being calibrated the error range is about +/-10mv.

BUG=b:131391176
TEST=make clean && make test-abuild; boots on Kukui rev 2 units.
BRANCH=none

Change-Id: Iccd6ea0ad810c993f9b62c0974279c960f890e52
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32800
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: JG Poxu <jg_poxu@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
jg_poxu 2019-05-15 11:36:45 +08:00 committed by Patrick Georgi
parent 8d83c662c3
commit a2c6a09985
3 changed files with 67 additions and 1 deletions

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@ -18,11 +18,37 @@
#include <delay.h> #include <delay.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>
#include <soc/auxadc.h> #include <soc/auxadc.h>
#include <soc/efuse.h>
#include <soc/infracfg.h> #include <soc/infracfg.h>
#include <timer.h> #include <timer.h>
static struct mtk_auxadc_regs *const mtk_auxadc = (void *)AUXADC_BASE; static struct mtk_auxadc_regs *const mtk_auxadc = (void *)AUXADC_BASE;
#define ADC_GE_A_SHIFT 10
#define ADC_GE_A_MASK (0x3ff << ADC_GE_A_SHIFT)
#define ADC_OE_A_SHIFT 0
#define ADC_OE_A_MASK (0x3ff << ADC_OE_A_SHIFT)
#define ADC_CALI_EN_A_SHIFT 20
#define ADC_CALI_EN_A_MASK (0x1 << ADC_CALI_EN_A_SHIFT)
static int cali_oe;
static int cali_ge;
static int calibrated = 0;
static void mt_auxadc_update_cali(void)
{
uint32_t cali_reg;
int cali_ge_a;
int cali_oe_a;
cali_reg = read32(&mtk_efuse->adc_cali_reg);
if ((cali_reg & ADC_CALI_EN_A_MASK) != 0) {
cali_oe_a = (cali_reg & ADC_OE_A_MASK) >> ADC_OE_A_SHIFT;
cali_ge_a = (cali_reg & ADC_GE_A_MASK) >> ADC_GE_A_SHIFT;
cali_ge = cali_ge_a - 512;
cali_oe = cali_oe_a - 512;
}
}
static uint32_t auxadc_get_rawdata(int channel) static uint32_t auxadc_get_rawdata(int channel)
{ {
setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10); setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10);
@ -44,8 +70,17 @@ static uint32_t auxadc_get_rawdata(int channel)
int auxadc_get_voltage(unsigned int channel) int auxadc_get_voltage(unsigned int channel)
{ {
uint32_t raw_value;
assert(channel < 16); assert(channel < 16);
if (!calibrated) {
mt_auxadc_update_cali();
calibrated = 1;
}
/* 1.5V in 4096 steps */ /* 1.5V in 4096 steps */
return (int)((int64_t)auxadc_get_rawdata(channel) * 1500000 / 4096); raw_value = auxadc_get_rawdata(channel);
raw_value = raw_value - cali_oe;
return (int)((int64_t)raw_value * 1500000 / (4096 + cali_ge));
} }

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@ -50,6 +50,7 @@ enum {
IOCFG_LB_BASE = IO_PHYS + 0x01E70000, IOCFG_LB_BASE = IO_PHYS + 0x01E70000,
IOCFG_LM_BASE = IO_PHYS + 0x01E80000, IOCFG_LM_BASE = IO_PHYS + 0x01E80000,
IOCFG_BL_BASE = IO_PHYS + 0x01E90000, IOCFG_BL_BASE = IO_PHYS + 0x01E90000,
EFUSEC_BASE = IO_PHYS + 0x01F10000,
IOCFG_LT_BASE = IO_PHYS + 0x01F20000, IOCFG_LT_BASE = IO_PHYS + 0x01F20000,
IOCFG_TL_BASE = IO_PHYS + 0x01F30000, IOCFG_TL_BASE = IO_PHYS + 0x01F30000,
SSUSB_SIF_BASE = IO_PHYS + 0x01F40300, SSUSB_SIF_BASE = IO_PHYS + 0x01F40300,

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@ -0,0 +1,30 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MTK_EFUSE_H
#define _MTK_EFUSE_H
#include <soc/addressmap.h>
#include <types.h>
struct efuse_regs {
uint32_t rserved[109];
uint32_t adc_cali_reg;
};
check_member(efuse_regs, adc_cali_reg, 0x1b4);
static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE;
#endif