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nb/intel/x4x: Rename a things that are not specific to DDR2 

This memory controller supports both DDR2 and DDR3 memory, yet many
functions have ddr2 in their name while not being ddr2 specific.
This patch renames those to avoid confusion.

Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2017-05-15 10:13:36 +02:00 committed by Patrick Georgi
parent 1848ba3b54
commit a2cc23169a
4 changed files with 30 additions and 40 deletions
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2
src/northbridge/intel/x4x/Makefile.inc
View File

@ -18,7 +18,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y)
romstage-y += early_init.c romstage-y += early_init.c
romstage-y += raminit.c romstage-y += raminit.c
romstage-y += raminit_ddr2.c romstage-y += raminit_ddr23.c
romstage-y += ram_calc.c romstage-y += ram_calc.c
romstage-y += rcven.c romstage-y += rcven.c
romstage-y += raminit_tables.c romstage-y += raminit_tables.c

12
src/northbridge/intel/x4x/raminit.c
View File

@ -674,17 +674,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
find_dimm_config(&s); find_dimm_config(&s);
} }
switch (s.spd_type) { do_raminit(&s, fast_boot);
case DDR2:
raminit_ddr2(&s, fast_boot);
break;
case DDR3:
// FIXME Add: raminit_ddr3(&s);
break;
default:
die("Unknown DDR type\n");
break;
}
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80);

54
src/northbridge/intel/x4x/raminit_ddr2.c → src/northbridge/intel/x4x/raminit_ddr23.c
View File

@ -48,7 +48,8 @@ u32 ddr2mhz(u32 speed)
return mhz[speed]; return mhz[speed];
} }
static void clkcross_ddr2(struct sysinfo *s)
static void program_crossclock(struct sysinfo *s)
{ {
u8 i, j; u8 i, j;
MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15); MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15);
@ -132,7 +133,7 @@ static void clkcross_ddr2(struct sysinfo *s)
MCHBAR32(0x70c) = clkxtab[i][j][12]; MCHBAR32(0x70c) = clkxtab[i][j][12];
} }
static void setioclk_ddr2(struct sysinfo *s) static void setioclk_dram(struct sysinfo *s)
{ {
MCHBAR32(0x1bc) = 0x08060402; MCHBAR32(0x1bc) = 0x08060402;
MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x200; MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x200;
@ -160,7 +161,7 @@ static void setioclk_ddr2(struct sysinfo *s)
MCHBAR32(0x994) = MCHBAR32(0x994) | (1 << 31); MCHBAR32(0x994) = MCHBAR32(0x994) | (1 << 31);
} }
static void launch_ddr2(struct sysinfo *s) static void launch_dram(struct sysinfo *s)
{ {
u8 i; u8 i;
u32 launch1 = 0x58001117; u32 launch1 = 0x58001117;
@ -346,7 +347,7 @@ void rt_set_dqs(u8 channel, u8 lane, u8 rank,
MCHBAR16(0x542 + 0x400 * channel + lane * 4) = saved_pi; MCHBAR16(0x542 + 0x400 * channel + lane * 4) = saved_pi;
} }
static void timings_ddr2(struct sysinfo *s) static void program_timings(struct sysinfo *s)
{ {
u8 i; u8 i;
u8 twl, ta1, ta2, ta3, ta4; u8 twl, ta1, ta2, ta3, ta4;
@ -571,7 +572,7 @@ static void timings_ddr2(struct sysinfo *s)
MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2; MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2;
} }
static void dll_ddr2(struct sysinfo *s) static void program_dll(struct sysinfo *s)
{ {
u8 i, j, r, reg8, clk, async = 0; u8 i, j, r, reg8, clk, async = 0;
u16 reg16 = 0; u16 reg16 = 0;
@ -853,7 +854,7 @@ static void set_all_dq_dqs_dll_settings(struct sysinfo *s)
} }
} }
static void rcomp_ddr2(struct sysinfo *s) static void prog_rcomp(struct sysinfo *s)
{ {
u8 i, j, k; u8 i, j, k;
u32 x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A, u32 x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A,
@ -924,7 +925,7 @@ static void rcomp_ddr2(struct sysinfo *s)
MCHBAR8(0x130) = MCHBAR8(0x130) | 1; MCHBAR8(0x130) = MCHBAR8(0x130) | 1;
} }
static void odt_ddr2(struct sysinfo *s) static void program_odt(struct sysinfo *s)
{ {
u8 i; u8 i;
u16 odt[16][2] = { u16 odt[16][2] = {
@ -1146,7 +1147,7 @@ static void sdram_program_receive_enable(struct sysinfo *s, int fast_boot)
rcven(s); rcven(s);
} }
static void dradrb_ddr2(struct sysinfo *s) static void set_dradrb(struct sysinfo *s)
{ {
u8 map, i, ch, r, rankpop0, rankpop1; u8 map, i, ch, r, rankpop0, rankpop1;
u32 c0dra = 0; u32 c0dra = 0;
@ -1320,7 +1321,7 @@ static void dradrb_ddr2(struct sysinfo *s)
MCHBAR16(0x10a) = dual_channel_size / 2; MCHBAR16(0x10a) = dual_channel_size / 2;
} }
static void mmap_ddr2(struct sysinfo *s) static void configure_mmap(struct sysinfo *s)
{ {
bool reclaim; bool reclaim;
u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud;
@ -1380,7 +1381,7 @@ static void mmap_ddr2(struct sysinfo *s)
pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20); pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);
} }
static void enhanced_ddr2(struct sysinfo *s) static void set_enhanced_mode(struct sysinfo *s)
{ {
u8 ch, reg8; u8 ch, reg8;
@ -1420,7 +1421,7 @@ static void enhanced_ddr2(struct sysinfo *s)
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~1); pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~1);
} }
static void power_ddr2(struct sysinfo *s) static void power_settings(struct sysinfo *s)
{ {
u32 reg1, reg2, reg3, reg4, clkgate, x592; u32 reg1, reg2, reg3, reg4, clkgate, x592;
u8 lane, ch; u8 lane, ch;
@ -1530,7 +1531,7 @@ static void power_ddr2(struct sysinfo *s)
MCHBAR8(0x561 + (lane << 2)) = MCHBAR8(0x561 + (lane << 2)) & ~(1 << 3); MCHBAR8(0x561 + (lane << 2)) = MCHBAR8(0x561 + (lane << 2)) & ~(1 << 3);
} }
void raminit_ddr2(struct sysinfo *s, int fast_boot) void do_raminit(struct sysinfo *s, int fast_boot)
{ {
u8 ch; u8 ch;
u8 r, bank; u8 r, bank;
@ -1558,37 +1559,36 @@ void raminit_ddr2(struct sysinfo *s, int fast_boot)
} }
// Program clock crossing // Program clock crossing
clkcross_ddr2(s); program_crossclock(s);
printk(BIOS_DEBUG, "Done clk crossing\n"); printk(BIOS_DEBUG, "Done clk crossing\n");
// DDR2 IO
if (s->boot_path != BOOT_PATH_WARM_RESET) { if (s->boot_path != BOOT_PATH_WARM_RESET) {
setioclk_ddr2(s); setioclk_dram(s);
printk(BIOS_DEBUG, "Done I/O clk\n"); printk(BIOS_DEBUG, "Done I/O clk\n");
} }
// Grant to launch // Grant to launch
launch_ddr2(s); launch_dram(s);
printk(BIOS_DEBUG, "Done launch\n"); printk(BIOS_DEBUG, "Done launch\n");
// Program DDR2 timings // Program DRAM timings
timings_ddr2(s); program_timings(s);
printk(BIOS_DEBUG, "Done timings\n"); printk(BIOS_DEBUG, "Done timings\n");
// Program DLL // Program DLL
dll_ddr2(s); program_dll(s);
if (!fast_boot) if (!fast_boot)
select_default_dq_dqs_settings(s); select_default_dq_dqs_settings(s);
set_all_dq_dqs_dll_settings(s); set_all_dq_dqs_dll_settings(s);
// RCOMP // RCOMP
if (s->boot_path != BOOT_PATH_WARM_RESET) { if (s->boot_path != BOOT_PATH_WARM_RESET) {
rcomp_ddr2(s); prog_rcomp(s);
printk(BIOS_DEBUG, "RCOMP\n"); printk(BIOS_DEBUG, "RCOMP\n");
} }
// ODT // ODT
odt_ddr2(s); program_odt(s);
printk(BIOS_DEBUG, "Done ODT\n"); printk(BIOS_DEBUG, "Done ODT\n");
// RCOMP update // RCOMP update
@ -1650,7 +1650,7 @@ void raminit_ddr2(struct sysinfo *s, int fast_boot)
printk(BIOS_DEBUG, "Done post-jedec\n"); printk(BIOS_DEBUG, "Done post-jedec\n");
// Set DDR2 init complete // Set DDR init complete
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
MCHBAR32(0x400*ch + 0x268) = (MCHBAR32(0x400*ch + 0x268) & ~0xc0000000) | 0xc0000000; MCHBAR32(0x400*ch + 0x268) = (MCHBAR32(0x400*ch + 0x268) & ~0xc0000000) | 0xc0000000;
} }
@ -1704,15 +1704,15 @@ void raminit_ddr2(struct sysinfo *s, int fast_boot)
} }
// DRADRB // DRADRB
dradrb_ddr2(s); set_dradrb(s);
printk(BIOS_DEBUG, "Done DRADRB\n"); printk(BIOS_DEBUG, "Done DRADRB\n");
// Memory map // Memory map
mmap_ddr2(s); configure_mmap(s);
printk(BIOS_DEBUG, "Done memory map\n"); printk(BIOS_DEBUG, "Done memory map\n");
// Enhanced mode // Enhanced mode
enhanced_ddr2(s); set_enhanced_mode(s);
printk(BIOS_DEBUG, "Done enhanced mode\n"); printk(BIOS_DEBUG, "Done enhanced mode\n");
// Periodic RCOMP // Periodic RCOMP
@ -1722,7 +1722,7 @@ void raminit_ddr2(struct sysinfo *s, int fast_boot)
printk(BIOS_DEBUG, "Done PRCOMP\n"); printk(BIOS_DEBUG, "Done PRCOMP\n");
// Power settings // Power settings
power_ddr2(s); power_settings(s);
printk(BIOS_DEBUG, "Done power settings\n"); printk(BIOS_DEBUG, "Done power settings\n");
// ME related // ME related
@ -1740,5 +1740,5 @@ void raminit_ddr2(struct sysinfo *s, int fast_boot)
MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26);
} }
printk(BIOS_DEBUG, "Done ddr2\n"); printk(BIOS_DEBUG, "Done raminit\n");
} }

2
src/northbridge/intel/x4x/x4x.h
View File

@ -360,7 +360,7 @@ u32 decode_igd_memory_size(u32 gms);
u32 decode_igd_gtt_size(u32 gsm); u32 decode_igd_gtt_size(u32 gsm);
u8 decode_pciebar(u32 *const base, u32 *const len); u8 decode_pciebar(u32 *const base, u32 *const len);
void sdram_initialize(int boot_path, const u8 *spd_map); void sdram_initialize(int boot_path, const u8 *spd_map);
void raminit_ddr2(struct sysinfo *s, int fast_boot); void do_raminit(struct sysinfo *, int fast_boot);
void rcven(struct sysinfo *s); void rcven(struct sysinfo *s);
u32 fsb2mhz(u32 speed); u32 fsb2mhz(u32 speed);
u32 ddr2mhz(u32 speed); u32 ddr2mhz(u32 speed);