mb/google/sarien: Enable LTR for PCIe NVMe root port
Enable LTR for NVMe so it can use ASPM L1.2. BUG=b:127593309 TEST=build and boot on sarien and check L1 substate with lspci before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ after: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ Change-Id: I9842beda6767f758556747f83cfcedbd00612698 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
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@ -196,6 +196,7 @@ chip soc/intel/cannonlake
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# PCIe port 13 for M.2 2280 SSD
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# PCIe port 13 for M.2 2280 SSD
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register "PcieRpEnable[12]" = "1"
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register "PcieRpEnable[12]" = "1"
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register "PcieRpLtrEnable[12]" = "1"
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register "PcieClkSrcUsage[4]" = "12"
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register "PcieClkSrcUsage[4]" = "12"
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register "PcieClkSrcClkReq[4]" = "4"
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register "PcieClkSrcClkReq[4]" = "4"
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@ -197,6 +197,7 @@ chip soc/intel/cannonlake
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# PCIe port 13 for M.2 2280 SSD
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# PCIe port 13 for M.2 2280 SSD
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register "PcieRpEnable[12]" = "1"
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register "PcieRpEnable[12]" = "1"
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register "PcieRpLtrEnable[12]" = "1"
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register "PcieClkSrcUsage[2]" = "12"
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register "PcieClkSrcUsage[2]" = "12"
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register "PcieClkSrcClkReq[2]" = "2"
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register "PcieClkSrcClkReq[2]" = "2"
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