sb/intel/lynxpoint: Use common final SPI OPs setup
Change-Id: I12e238b3a33c909103986822bd7398e1c3bac676 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -36,6 +36,7 @@
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#include <drivers/intel/gma/i915.h>
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#include <southbridge/intel/common/acpi_pirq_gen.h>
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#include <southbridge/intel/common/rtc.h>
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#include <southbridge/intel/common/spi.h>
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#define NMI_OFF 0
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@ -960,10 +961,7 @@ static unsigned long southbridge_write_acpi_tables(struct device *device,
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static void lpc_final(struct device *dev)
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{
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RCBA16(0x3894) = SPI_OPPREFIX;
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RCBA16(0x3896) = SPI_OPTYPE;
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RCBA32(0x3898) = SPI_OPMENU_LOWER;
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RCBA32(0x389c) = SPI_OPMENU_UPPER;
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spi_finalize_ops();
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if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN))
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outb(APM_CNT_FINALIZE, APM_CNT);
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@ -746,42 +746,6 @@ void mainboard_config_superio(void);
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#define FDOC 0xb0
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#define FDOD 0xb4
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#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
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#define SPI_OPTYPE_0 0x01 /* Write, no address */
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#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
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#define SPI_OPTYPE_1 0x03 /* Write, address required */
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#define SPI_OPMENU_2 0x03 /* READ: Read Data */
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#define SPI_OPTYPE_2 0x02 /* Read, address required */
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#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
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#define SPI_OPTYPE_3 0x00 /* Read, no address */
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#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
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#define SPI_OPTYPE_4 0x03 /* Write, address required */
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#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
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#define SPI_OPTYPE_5 0x00 /* Read, no address */
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#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
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#define SPI_OPTYPE_6 0x03 /* Write, address required */
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#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
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#define SPI_OPTYPE_7 0x02 /* Read, address required */
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#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
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(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
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#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
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(SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
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#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
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(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
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(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
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(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
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#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
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#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */
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#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
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#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
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