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mb/amd/onyx: Add MPIO config 

Add the device and chip entries for the various PCIe ports and MPIO
lane configuration. Below each PCIe bridge device with an external PCIe
port on the mainboard, an MPIO chip is added that provides the
corresponding MPIO configuration for this external PCIe port.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8563c5a07eb8fd8ff9dd4e7b63fc9a7d485b1316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78921
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2023-09-27 17:14:42 -06:00 committed by Felix Held
parent f1b1412068
commit a31b28cb23
1 changed files with 121 additions and 0 deletions
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121
src/mainboard/amd/onyx/devicetree.cb
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@ -53,6 +53,127 @@ chip soc/amd/genoa
}" }"
device domain 0 on device domain 0 on
device ref gpp_bridge_0_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P2
register "start_lane" = "48"
register "end_lane" = "63"
register "gpio_group" = "1"
register "aspm" = "L1"
device generic 0 on end # dummy for configuring mpio
end
end
device ref gpp_bridge_0_0_b on
chip vendorcode/amd/opensil/genoa_poc/mpio # G2
register "start_lane" = "112"
register "end_lane" = "127"
register "gpio_group" = "1"
register "aspm" = "L1"
register "hotplug" = "ServerExpress"
device generic 0 on end
end
end
device ref gpp_bridge_0_0_c on
chip vendorcode/amd/opensil/genoa_poc/mpio
register "start_lane" = "128"
register "end_lane" = "131"
register "gpio_group" = "1"
register "aspm" = "L1"
device generic 0 on end
end
end
end
device domain 1 on
device ref gpp_bridge_1_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P3
register "start_lane" = "16"
register "end_lane" = "31"
register "gpio_group" = "1"
register "aspm" = "L1"
device generic 0 on end
end
end
device ref gpp_bridge_1_0_b on
chip vendorcode/amd/opensil/genoa_poc/mpio # G3
register "start_lane" = "80"
register "end_lane" = "95"
register "gpio_group" = "1"
register "aspm" = "L1"
device generic 0 on end
end
end
end
device domain 2 on
device ref gpp_bridge_2_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P1
register "start_lane" = "32"
register "end_lane" = "47"
register "gpio_group" = "1"
register "aspm" = "L1"
register "hotplug" = "ServerExpress"
device generic 0 on end
end
end
device ref gpp_bridge_2_0_b on
chip vendorcode/amd/opensil/genoa_poc/mpio # G1
register "start_lane" = "64"
register "end_lane" = "79"
register "gpio_group" = "1"
register "aspm" = "L1"
device generic 0 on end
end
end
end
device domain 3 on
device ref gpp_bridge_3_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P0
register "start_lane" = "0"
register "end_lane" = "15"
register "gpio_group" = "1"
register "aspm" = "L1"
device generic 0 on end
end
end
device ref gpp_bridge_3_0_b on
chip vendorcode/amd/opensil/genoa_poc/mpio # G0
register "start_lane" = "96"
register "end_lane" = "111"
register "gpio_group" = "1"
register "aspm" = "L1"
device generic 0 on end
end
end
device ref gpp_bridge_3_0_c on # WAFL
chip vendorcode/amd/opensil/genoa_poc/mpio
register "start_lane" = "132"
register "end_lane" = "133"
register "gpio_group" = "1"
register "aspm" = "L1"
device generic 0 on end
end
end
device ref gpp_bridge_3_1_c on # BMC
chip vendorcode/amd/opensil/genoa_poc/mpio
register "start_lane" = "134"
register "end_lane" = "134"
register "gpio_group" = "1"
register "aspm" = "L1"
register "bmc" = "1"
device generic 0 on end
end
end
device ref gpp_bridge_3_2_c on # BMC
chip vendorcode/amd/opensil/genoa_poc/mpio
register "start_lane" = "135"
register "end_lane" = "135"
register "gpio_group" = "1"
register "aspm" = "L1"
device generic 0 on end
end
end
end end
end end