soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I69466143315c1c9870a97c9ef8f68ed85f38e779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50415 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -65,6 +65,13 @@ void global_smi_enable(void)
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smi_write32(SMI_REG_SMITRIG0, reg);
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smi_write32(SMI_REG_SMITRIG0, reg);
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}
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}
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void southbridge_smi_set_eos(void)
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{
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uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
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reg |= SMITRG0_EOS;
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smi_write32(SMI_REG_SMITRIG0, reg);
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}
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void soc_route_sci(uint8_t event)
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void soc_route_sci(uint8_t event)
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{
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{
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smi_write8(SMI_SCI_MAP(event), event);
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smi_write8(SMI_SCI_MAP(event), event);
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@ -293,10 +293,3 @@ void southbridge_smi_handler(void)
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if (smi_src & SMI_STATUS_SRC_4)
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if (smi_src & SMI_STATUS_SRC_4)
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process_smi_sources(SMI_REG_SMISTS4);
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process_smi_sources(SMI_REG_SMISTS4);
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}
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}
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void southbridge_smi_set_eos(void)
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{
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uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
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reg |= SMITRG0_EOS;
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smi_write32(SMI_REG_SMITRIG0, reg);
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}
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@ -288,10 +288,3 @@ void southbridge_smi_handler(void)
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if (smi_src & SMI_STATUS_SRC_4)
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if (smi_src & SMI_STATUS_SRC_4)
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process_smi_sources(SMI_REG_SMISTS4);
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process_smi_sources(SMI_REG_SMISTS4);
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}
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}
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void southbridge_smi_set_eos(void)
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{
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uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
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reg |= SMITRG0_EOS;
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smi_write32(SMI_REG_SMITRIG0, reg);
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}
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