GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

RS780 function ProgK8TempMmioBase is setting a reserved 

bit in the AMD processor 'MMIO Limit Address Register'.
I suspect it is because of a typo where 0x80 was entered
as 0x8. If 0x80 is used, then the strap configuration
register accesses become non-posted, which is how the
Shiner reference BIOS does it.


Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2010-10-07 18:25:04 +00:00 committed by Rudolf Marek
parent 6798b47802
commit a3bd1b1b25
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/amd/rs690/rs690_cmn.c
View File

@ -206,7 +206,7 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
if (in_out) {
pci_write_config32(k8_f1, 0xbc,
(((pcie_base_add + 0x10000000 -
1) >> 8) & 0xffffff00) | 0x8);
1) >> 8) & 0xffffff00) | 0x80);
pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
pci_write_config32(k8_f1, 0xb4,
((mmio_base_add + 0x10000000 -

2
src/southbridge/amd/rs780/rs780_cmn.c
View File

@ -204,7 +204,7 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
if (in_out) {
pci_write_config32(k8_f1, 0xbc,
(((pcie_base_add + 0x10000000 -
1) >> 8) & 0xffffff00) | 0x8);
1) >> 8) & 0xffffff00) | 0x80);
pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
pci_write_config32(k8_f1, 0xb4,
((mmio_base_add + 0x10000000 -