cpu/amd/{agesa,pi}/Kconfig: select SSE2
SSE2 instructions are supported by family14 and newer. SSE will be automatically enabled in bootblock_crt0 for platforms that migrate to C bootblock. Because of that family specific CAR setup may avoid additional code. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37292 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
f3db2aea85
commit
a3ce27d3dd
|
@ -29,6 +29,7 @@ config CPU_AMD_AGESA
|
||||||
select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME
|
select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME
|
||||||
select SMM_ASEG
|
select SMM_ASEG
|
||||||
select NO_FIXED_XIP_ROM_SIZE
|
select NO_FIXED_XIP_ROM_SIZE
|
||||||
|
select SSE2
|
||||||
|
|
||||||
if CPU_AMD_AGESA
|
if CPU_AMD_AGESA
|
||||||
|
|
||||||
|
|
|
@ -28,6 +28,7 @@ config CPU_AMD_PI
|
||||||
select SPI_FLASH if HAVE_ACPI_RESUME
|
select SPI_FLASH if HAVE_ACPI_RESUME
|
||||||
select SMM_ASEG
|
select SMM_ASEG
|
||||||
select NO_FIXED_XIP_ROM_SIZE
|
select NO_FIXED_XIP_ROM_SIZE
|
||||||
|
select SSE2
|
||||||
|
|
||||||
if CPU_AMD_PI
|
if CPU_AMD_PI
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue