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Make the pll stuff parameterized. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2006-03-14 20:01:51 +00:00
parent c994c973c6
commit a41ff52ba9
2 changed files with 8 additions and 4 deletions
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4
src/mainboard/amd/rumba/auto.c
View File

@ -40,6 +40,10 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
#include "northbridge/amd/gx2/raminit.c" #include "northbridge/amd/gx2/raminit.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
#define PLLMSRhi 0x00001490
#define PLLMSRlo 0x02000030
#define PLLMSRhi2 ((0xde << 16) | (1 << 26) | (1 << 24))
#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
#include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/pll_reset.c"
static void msr_init(void) static void msr_init(void)

8
src/northbridge/amd/gx2/pll_reset.c
View File

@ -133,15 +133,15 @@ static void pll_reset(void)
if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) { if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
print_debug("disable PLL bypass\n\r"); print_debug("disable PLL bypass\n\r");
msr.hi = 0x00001490; msr.hi = PLLMSRhi;
msr.lo = 0x02000030; msr.lo = PLLMSRlo;
wrmsr(GLCP_SYS_RSTPLL, msr); wrmsr(GLCP_SYS_RSTPLL, msr);
msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24)); msr.lo |= PLLMSRhi2;
wrmsr(GLCP_SYS_RSTPLL, msr); wrmsr(GLCP_SYS_RSTPLL, msr);
print_debug("Reset PLL\n\r"); print_debug("Reset PLL\n\r");
msr.lo |= ((1<<14) |(1<<13) | (1<<0)); msr.lo |= PLLMSRlo2;
wrmsr(GLCP_SYS_RSTPLL,msr); wrmsr(GLCP_SYS_RSTPLL,msr);
print_debug("should not be here\n\r"); print_debug("should not be here\n\r");
} }