Add a new CMOS variable which triggers activation of the
LPT port. With the CMOS variable set, LPT is found by SeaBIOS, with the variable reset, it's not. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -93,7 +93,8 @@ entries
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416 512 s 0 boot_devices
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928 8 h 0 boot_default
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936 1 e 8 cmos_defaults_loaded
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#937 47 r 0 unused
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937 1 e 1 lpt
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#938 46 r 0 unused
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# coreboot config options: check sums
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984 16 h 0 check_sum
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@ -86,7 +86,9 @@ chip northbridge/intel/i945
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device pnp 2e.1 off # ACPI PM
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end
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# 2e.2 does not exist
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device pnp 2e.3 off # Parallel port
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 5
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end
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device pnp 2e.4 on # COM1
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io 0x60 = 0x3f8
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@ -34,6 +34,7 @@
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#include "northbridge/intel/i945/i945.h"
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#include "northbridge/intel/i945/raminit.h"
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#include "southbridge/intel/i82801gx/i82801gx.h"
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#include "option_table.h"
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void setup_ich7_gpios(void)
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{
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@ -81,12 +82,16 @@ void setup_ich7_gpios(void)
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static void ich7_enable_lpc(void)
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{
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int lpt_en = 0;
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if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
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lpt_en = 1<<2; // enable LPT
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}
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// Enable Serial IRQ
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
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// decode range
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
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// decode range
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
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// Enable 0x02e0 - 0x2ff
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1);
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// Enable 0x600 - 0x6ff
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@ -104,8 +104,9 @@ entries
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968 1 e 2 ethernet1
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969 1 e 2 ethernet2
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970 1 e 2 ethernet3
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971 1 e 1 lpt
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#971 13 r 0 unused
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#972 12 r 0 unused
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# coreboot config options: check sums
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984 16 h 0 check_sum
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@ -52,7 +52,9 @@ chip northbridge/intel/i945
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chip superio/winbond/w83627thg
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device pnp 2e.0 off # Floppy
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end
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device pnp 2e.1 off # Parport
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device pnp 2e.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 5
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end
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device pnp 2e.2 on
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io 0x60 = 0x3f8
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@ -58,12 +58,16 @@ void setup_ich7_gpios(void)
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static void ich7_enable_lpc(void)
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{
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int lpt_en = 0;
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if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
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lpt_en = 1<<2; // enable LPT
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}
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// Enable Serial IRQ
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
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// Set COM1/COM2 decode range
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
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// Enable COM1/COM2/KBD/SuperIO1+2
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en);
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// Enable HWM at 0xa00
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
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// COM3 decode
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@ -93,7 +93,8 @@ entries
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416 512 s 0 boot_devices
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928 8 h 0 boot_default
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936 1 e 8 cmos_defaults_loaded
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#937 47 r 0 unused
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937 1 e 1 lpt
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#938 46 r 0 unused
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# coreboot config options: check sums
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984 16 h 0 check_sum
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@ -83,7 +83,9 @@ chip northbridge/intel/i945
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#device pci 1e.3 off end # AC'97 Modem
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device pci 1f.0 on # LPC bridge
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chip superio/smsc/lpc47n227
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device pnp 2e.1 off # Parallel port
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device pnp 2e.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 5
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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@ -36,6 +36,7 @@
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#include "northbridge/intel/i945/i945.h"
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#include "northbridge/intel/i945/raminit.h"
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#include "southbridge/intel/i82801gx/i82801gx.h"
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#include "option_table.h"
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void setup_ich7_gpios(void)
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{
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static void ich7_enable_lpc(void)
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{
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int lpt_en = 0;
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if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
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lpt_en = 1<<2; // enable LPT
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}
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// Enable Serial IRQ
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
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// decode range
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
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// decode range
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
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// Enable 0x02e0
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1);
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c);
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